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Title: US4999803: Floating point arithmetic system and method
[ Derwent Title ]


Country: US United States of America

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Inventor: Turrini, Silvio; Trieste, Italy
Leonard, Judson S.; Waban, MA
Jouppi, Norman P.; Palo Alto, CA

Assignee: Digital Equipment Corporation, Maynard, MA
other patents from DIGITAL EQUIPMENT CORPORATION (147695) (approx. 2,345)
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Published / Filed: 1991-03-12 / 1989-06-29

Application Number: US1989000374164

IPC Code: Advanced: G06F 7/485; G06F 7/50;
Core: more...
IPC-7: G06F 7/38;

ECLA Code: G06F7/485; S06F207/38A6P;

U.S. Class: Current: 708/505;
Original: 364/748;

Field of Search: 364/748,715.04,715.08

Priority Number:
1989-06-29  US1989000374164

Abstract:     System and method for reducing the processing time or latency of floating point arithmetic operations by eliminating the need to complement a negative result produced by a subtraction operation. Each of two numbers is subtracted from the other in simultaneous parallel subtraction operations to produce one answer which is positive and one answer which is negative. The answer which is positive is selected as the result of the operation.

Attorney, Agent or Firm: Flehr, Hohbach, Test, Albritton & Herbert ;

Primary / Asst. Examiners: Shaw, Dale M.; Mai, Tan V.

INPADOC Legal Status: Show legal status actions

Family: None

First Claim:
Show all 4 claims
We claim:     1. In a system for performing floating point arithmetic with first and second numbers each having a mantissa and an exponent:
  • a. means for comparing the exponents of the two numbers;
  • b. a first data path having an alignment shifter for shifting the mantissa of one of the numbers by more than one place to provide numbers with aligned mantissas and equal exponents, an adder/subtractor for combining the aligned mantissas, and means for normalizing the output from the adder/subtractor by shifting its mantissa by no more than one place;
  • c. a second data path having means for shifting the mantissa of one of the two numbers no more than one place to provide numbers with aligned mantissas and equal exponents, a pair of subtractors in parallel paths for simultaneously subtracting the mantissa of the first number from the mantissa of the second number and the mantissa of the second number from the mantissa of the first number to produce one result which is positive and one result which is negative, means for selecting the positive result, and means for normalizing the selected result by shifting its mantissa by more than one place; and
  • d. means for selecting between the normalized results from the two data paths.


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Forward References: Show 15 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (15)   |   Backward references (13)   |   Citation Link

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Patent  Pub.Date  Inventor Assignee   Title
  US3697734  1972-10 Booth et al.  The Singer Company DIGITAL COMPUTER UTILIZING A PLURALITY OF PARALLEL ASYNCHRONOUS ARITHMETIC UNITS
Buy PDF- 10pp US3814925  1974-06 Spannagel  Amdahl Corporation DUAL OUTPUT ADDER AND METHOD OF ADDITION FOR CONCURRENTLY FORMING THE DIFFERENCES A-B AND B-A
Buy PDF- 35pp US4229801  1980-10 Whipple  Data General Corporation Floating point processor having concurrent exponent/mantissa operation
Buy PDF- 15pp US4295203  1981-10 Joyce  Honeywell Information Systems Inc. Automatic rounding of floating point operands
Buy PDF- 16pp US4308589  1981-12 Joyce et al.  Honeywell Information Systems Inc. Apparatus for performing the scientific add instruction
Buy PDF- 13pp US4488252  1984-12 Vassar  Raytheon Company Floating point addition architecture
Buy PDF- 10pp US4562553  1985-12 Mattedi et al.  Analogic Corporation Floating point arithmetic system and method with rounding anticipation
Buy PDF- 13pp US4639887  1987-01 Farmwald  The United States of America as represented by the United States Department of Energy Bifurcated method and apparatus for floating point addition with decreased latency time
Buy PDF- 12pp US4683546  1987-07 Boney  Motorola, Inc. Floating point condition code generation
Buy PDF- 6pp US4719589  1988-01 Tanaka  NEC Corporation Floating-point adder circuit
Buy PDF- 14pp US4720809  1988-01 Taylor  University of Florida Hybrid floating point/logarithmic number system arithmetic processor
Buy PDF- 16pp US4807172  1989-02 Nukiyama  NEC Corporation Variable shift-count bidirectional shift control circuit
Buy PDF- 9pp US4811272  1989-03 Wolrich et al.  Digital Equipment Corporation Apparatus and method for an extended arithmetic logic unit for expediting selected floating point operations
       
Foreign References: None

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