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 Title: |
US5111076:
Digital superbuffer
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| Country: |
US United States of America
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| Inventor: |
Tarng, Min Ming; San Jose, CA 95129
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| Assignee: |
None
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| Published / Filed: |
1992-05-05
/ 1990-09-05
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| Application Number: |
US1990000577791
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| IPC Code: |
Advanced:
H03K 19/003;
H03K 19/094;
Core:
more...
IPC-7:
H03K 17/16;
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| U.S. Class: |
Current:
326/027;
326/033;
326/058;
326/083;
326/084;
327/323;
Original:
307/446;
307/443;
307/554;
307/562;
307/451;
307/496;
307/497;
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| Field of Search: |
307/554,562,451,494,496,497,296.1,296.8,475,446,443
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| Priority Number: |
| 1990-09-05 |
US1990000577791 |
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| Abstract: |
The output buffer uses the output feedback control to control the transmission speed of the input signal. With the output feedback control, the NMOS and PMOS has the different switching speed. As the output node switches from 0 to 1 state, the NMOS turns off before the turning on of PMOS. As the output node switches from 1 state to 0 state, the PMOS turns off before the turning on of NMOS. There are the multiple functions: nonoverlapping switch, the soft-turn switch and the speed-up fast switch. The short current between the power and ground is eliminated; the ground bounce and the power surge are reduced.
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| Primary / Asst. Examiners: |
Miller, Stanley D.; Ouellette, Scott A.
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| Maintenance Status: |
E2 Expired Check current status
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| INPADOC Legal Status: |
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| Family: |
None
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First Claim:
Show all 17 claims |
What I claim is:
1. A buffer comprising
- a first and second supply voltages,
- an output stage comprising an output terminal, a first transistor connected between said output terminal and said first supply voltage, a second transistor connected between said output terminal and said second supply voltage,
- an input terminal,
- a first control means connected between said input terminal and said first transistor,
- a second control means connected between said input terminal and said second transistor,
- said first control means comprising a third transistor having a gate connected to said output terminal and forming a current path between said input terminal and a gate of said first transistor,
- said second control means comprising a fourth transistor having a gate connected to said output terminal and forming a current path between said input terminal and a gate of said second transistor.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 22 U.S. patent(s) that reference this one
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