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 Title: |
US5150469:
System and method for processor pipeline control by selective signal deassertion
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Jouppi, Norman P.; Palo Alto, CA
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| Assignee: |
Digital Equipment Corporation, Maynard, MA
other patents from DIGITAL EQUIPMENT CORPORATION (147695) (approx. 2,345)
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| Published / Filed: |
1992-09-22
/ 1990-07-13
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| Application Number: |
US1990000554131
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| IPC Code: |
Advanced:
G06F 9/30;
G06F 9/38;
Core:
more...
IPC-7:
G06F 9/30;
G06F 9/38;
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| U.S. Class: |
Current:
712/244;
712/E09.028;
712/E09.061;
712/E09.065;
712/E09.069;
Original:
395/375;
364/231.8;
364/228.6;
364/241.6;
364/263.2;
364/931.49;
364/933.2;
364/948.34;
364/941.7;
364/DIG.1;
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| Field of Search: |
395/375
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| Priority Number: |
| 1988-12-12 |
US1988000283499 |
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| Abstract: |
A processor pipeline control system and method provides a complete set of very simple and very fast pipeline control signals encompassing stalls and interrupts. Each pipeline stage has associated with it a signal called "LoadX", where X is the pipeline stage name, e.g., LoadID. Instead of signalling exceptional conditions in terms of the event, e.g., "cache miss", exceptional conditions are signalled within the processor by deasserting the LoadX signals required by that exception. When the pipeline control for one pipestage is deasserted, in order to prevent previous instructions from entering the stalled pipestage, the detector of the exceptional condition must deassert all LoadX control signals for stages previous to X as well.
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| Attorney, Agent or Firm: |
Flehr, Hohbach, Test, Albritton & Herbert ;
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| Primary / Asst. Examiners: |
Eng, David Y.; Kim, Ken S.
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| INPADOC Legal Status: |
Show legal status actions
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| Parent Case: |
This is a continuation of application Ser. No. 07/283,499 filed Dec. 12, 1988 now abandoned.
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| Family: |
None
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First Claim:
Show all 18 claims |
What is claimed is:
1. A system for processor pipeline control of a pipeline having a plurality of sequential pipestages, which comprises a means for generating a like plurality of pipeline control signals each corresponding to an action carried out in one of said plurality of sequential pipestages, the like plurality of pipeline control signals controlling whether each of said like plurality of sequential pipestages stalls or advances, and means, connected to said means for generating pipeline control signals, for selective deassertion of each one of the like plurality of pipeline control signals in response to an exceptional event requiring one of a stall and interruption of one of the plurality of sequential pipestages corresponding to a selected one of the like plurality of pipeline control signals, and for deasserting ones of the like plurality of pipeline control signals corresponding to all those of the plurality of sequential pipestages sequentially previous to the pipestage corresponding to the selected one of the like plurality of pipeline control signals, said means for selective deassertion being configured so that a first exceptional event causing a deassertion of the pipeline control signal for a later one of the like plurality of sequential pipestages necessarily includes deassertion of any pipeline control signal appropriate for a second exceptional event causing deassertion of a previous one of the like plurality of pipeline control signals for a previous pipestage, said system being free of pipeline control logic for prioritizing the exceptional events and to translate the exceptional events into control signals.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 41 U.S. patent(s) that reference this one
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