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 Title: |
US5198691:
BiMOS devices and BiMOS memories
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Tarng, Min M.; San Jose, CA 95129
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| Assignee: |
None
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| Published / Filed: |
1993-03-30
/ 1990-09-05
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| Application Number: |
US1990000577792
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| IPC Code: |
Advanced:
H01L 27/07;
H01L 27/11;
H01L 27/115;
Core:
more...
IPC-7:
H01L 27/04;
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| U.S. Class: |
Current:
257/316;
257/318;
257/370;
257/378;
257/E27.028;
257/E27.098;
257/E27.103;
365/185.1;
Original:
257/316;
257/370;
257/378;
257/318;
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| Field of Search: |
357/043,35,23.5,42
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| Priority Number: |
| 1989-04-10 |
US1989000335584 |
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| Abstract: |
The BiMOS devices are compact 3D devices having a coupled bipolar and MOS mechanisms integrated in one single cell. The gates cover over the bipolar regions. The bipolar regions are the tubs of the MOS mechanisms. The MOS mechanisms make the connection between the base, emitter and collector to charge and discharge the base voltage. The input applies on the gate to switch on/off the base current of the bipolar mechanism. There are P-PNP, N-NPN, N-PNP, P-NPN, PN-PNP, PN-NPN, NP-PNP and NP-NPN BiMOS devices. The BiMOS inverter, NOR, NAND logic gates are the single stage circuit having the same circuit configuration as CMOS circuits. They are made of P-PNP, N-NPN, NP-PNP and NP-NPN BiMOS devices. The digital BiMOS buffer, OR, AND logic gates are the single stage circuits made of N-PNP, P-NPN, PN-PNP and PN-NPN BiMOS devices. Furthermore, the BiMOS technologies are applied to SRAM, EPROM and EEPROM to generate the BiMOS SRAM, BiMOS EPROM and BiMOS EEPROM memory devices.
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| Primary / Asst. Examiners: |
Larkins, William D.;
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| Maintenance Status: |
E2 Expired Check current status
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| INPADOC Legal Status: |
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Family Legal Status Report
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| Parent Case: |
This is a continuation in part of application Ser. No. 07/335,584 filed Apr. 10, 1989, now abandoned.
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| Family: |
Show 2 known family members
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First Claim:
Show all 13 claims |
I claim:
1. A unitary bipolar/MOSFET transistor structure, comprising:
- a first semiconductor region of first conductivity type, said first semiconductor region having a major surface;
- second, third, and fourth regions of second conductivity type in said first region, said second, third, and fourth regions each adjoining said major surface, said third region being spaced from said second region by a first channel portion of said first region, said fourth region being spaced from said third region by a second channel portion of said first region, and said second and fourth regions being spaced apart from each other,
- a gate electrode insulatingly overlying both said first and said second channel portions,
- a substrate region of second conductivity type, said substrate region underlying said first semiconductor region and being spaced from said second region by a portion of said first region, so that said second region, said portion of said first region, and said substrate region form a bipolar transistor structure, said fourth region adjoining said substrate region so as to form a connection thereto;
- means for forming a low impedance connection between said third region and said first region;
- an emitter electrode connected to said second region and a collector electrode connected to said fourth region;
- whereby said structure forms an equivalent circuit comprising a bipolar transistor having said emitter and collector electrode as its respective main terminal, and with said first region as its base region, with a first effective insulated gate field effect transistor connected between said emitter electrode and said first region, and a second insulated gate field effect transistor connected between said first region and said collector electrode, said gate electrode controlling conduction of both field effect transistors, so that when an input voltage is applied between said gate electrode and one of said emitter and collector electrodes so as to render said first field effect transistor and said second field effect transistor conductive, said first and second insulated gate field effect transistors act as a voltage divider between said emitter and collector electrodes and provide a voltage to said first region with respect to said second region to cause said bipolar transistor to conduct.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 9 U.S. patent(s) that reference this one
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