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 Title: |
US5210856:
Non-aligned DRAM state machine for page-mode DRAM control
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Auvinen, Stuart; Santa Cruz, CA
Sowell, Richard; San Jose, CA
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| Assignee: |
Chips and Technologies, Inc., San Jose, CA
other patents from CHIPS & TECHNOLOGIES, LLC (765535) (approx. 81)
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| Published / Filed: |
1993-05-11
/ 1991-08-07
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| Application Number: |
US1991000741778
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| IPC Code: |
Advanced:
G11C 7/22;
Core:
G11C 7/00;
IPC-7:
G06F 1/04;
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| U.S. Class: |
Current:
713/400;
Original:
395/550;
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| Field of Search: |
364/DIG. 1,DIG. 2
395/164,165,550,275
307/269
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| Priority Number: |
| 1991-08-07 |
US1991000741778 |
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| Abstract: |
An apparatus and method for operating a system component in a microprocessor system. The component is operated by a component controller which runs off a clock having a frequency different than the system clock. The controller is synchronized with the system clock at the conclusion of a component access cycle. The state machine of the controller can thus operate independently of the system clock and timing options implemented by the controller need not have an even number of states.
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| Attorney, Agent or Firm: |
Townsend and Townsend ;
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| Primary / Asst. Examiners: |
Richardson, Robert L.;
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| Maintenance Status: |
E3 Expired Check current status
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| INPADOC Legal Status: |
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| Family: |
None
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First Claim:
Show all 11 claims |
What is claimed is:
1. In a microprocessor system including a microprocessor operating according to a first clock, and having a component controller operating according to a second clock having a frequency m times the frequency of the first clock, an apparatus for synchronizing said component controller to said first clock at the completion of a component access cycle comprising:
- means, coupled to a state machine of said component controller, and adapted to receive signals identifying an n-1 through n-m states of a component access cycle having n state transitions, for sampling for said n-1 through n-m states on a given edge of said first clock; and
- means, coupled to said means for sampling, for asserting a ready signal having a period of at least one first clock pulse to synchronize said component controller to said first clock, when one of said n-1 through n-m states is detected.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 7 U.S. patent(s) that reference this one
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