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 Title: |
US5261066:
Data processing system and method with small fully-associative cache and prefetch buffers
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Jouppi, Norman P.; Palo Alto, CA
Eustace, Alan; Palo Alto, CA
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| Assignee: |
Digital Equipment Corporation, Maynard, MA
other patents from DIGITAL EQUIPMENT CORPORATION (147695) (approx. 2,345)
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| Published / Filed: |
1993-11-09
/ 1990-03-27
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| Application Number: |
US1990000499958
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| IPC Code: |
Advanced:
G06F 12/08;
F02B 75/02;
Core:
more...
IPC-7:
G06F 12/00;
G06F 12/08;
G06F 13/00;
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| U.S. Class: |
Current:
711/122;
711/128;
711/E12.057;
Original:
395/425;
364/DIG.1;
364/243.45;
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| Field of Search: |
364/DIG. 1,DIG. 2,243,243.45,243.7,964,343,964.22,964.23,964.6,964.5
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| Priority Number: |
| 1990-03-27 |
US1990000499958 |
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| Abstract: |
A memory system (10) utilizes miss caching by incorporating a small fully-associative miss cache (42) between a cache (18 or 20) and second-level cache (26). misses in the cache (18 or 20) that hit in the miss cache have only a one cycle miss penalty, as opposed to a many cycle miss penalty without the miss cache (42). Victim caching is an improvement to miss caching that loads a small, fully associative cache (52) with the victim of a miss and not the requested line. Small victim caches (52) of 1 to 4 entries are even more effective at removing conflict misses than miss caching. Stream buffers (62) prefetch cache lines starting at a cache miss address. The prefetched data is placed in the buffer (62) and not in the cache (18 or 20). Stream buffers (62) are useful in removing capacity and compulsory cache misses, as well as some instruction cache misses. Stream buffers (62) are more effective than previously investigated prefetch techniques when the next slower level in the memory hierarchy is pipelined. An extension to the basic stream buffer, called multi-way stream buffers (62), is useful for prefetching along multiple intertwined data reference streams.
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| Attorney, Agent or Firm: |
Flehr, Hohbach, Test, Albritton & Herbert ;
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| Primary / Asst. Examiners: |
Bowler, Alyssa H.;
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| INPADOC Legal Status: |
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Family Legal Status Report
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| Designated Country: |
DE FR GB IT
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| Family: |
Show 9 known family members
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First Claim:
Show all 16 claims |
What is claimed is:
1. A memory system comprising:
- a first memory for storing information to be supplied to a processor, said first memory including a first direct-mapped cache memory and an associative cache memory coupled to said first direct-mapped cache memory, said associative cache memory having a substantially smaller memory capacity than said first direct-mapped cache memory;
- a second memory for storing information to be supplied to said processor through said first memory; and
- means, coupled to said first memory and said second memory, for addressing information and for supplying information from said second memory to said first direct-mapped cache memory and to said associative cache memory when a miss occurs in said first memory for addressed information, said means for addressing information and for supplying information being connected and configured to displace least recently used information in said associative cache memory with said information supplied to said first direct-mapped cache memory and to said associative cache memory and to supply information from said associative cache memory to said first direct-mapped cache memory when an address misses in said first direct-mapped cache memory and hits in said associative cache memory.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 130 U.S. patent(s) that reference this one
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