Apparatus and method for single operand register array for vector and scalar data processing operations (US5261113)


	Parent Case:			This is a continuation of copending application Ser. No. 07/147,754, filed on Jan. 25, 1988, now abandoned.
	Family:			None
	First Claim: Show all 16 claims			What is claimed is: 1. A central processing unit for performing scalar and vector data processing operations, said central processing unit comprising: an execution portion capable of performing vector processing operations and scalar processing operations in response to instructions having a format with a field of data bits to identify said vector processing operations and said scalar processing operations; means, responsive to a plurality of executing instructions, for providing control signals determined by said instructions; and operand register file means, responsive to control signals from said control signal means, for applying a first sequence and a second sequence of operands identified by one of said plurality of executing instructions to said execution portion, with said first and said second sequence of operands being stored in said operand register file means and with at least a first one of said first and second sequences of operands stored in said register file means having an operand corresponding to a scalar data processing operation and with at least a second one of said first and second sequences of operands having an operand corresponding to a vector data processing operation; and with said one of said plurality of said executing instructions causing processing operations identified by said one of said plurality of said executing instructions to be performed by said execution portion.
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	Forward References:			Show 11 U.S. patent(s) that reference this one

U.S. References:

Go to Result Set: All U.S. references | Forward references (11) | Backward references (20) | Citation Link

Patent	Pub.Date	Inventor	Assignee	Title
US3794984	1974-02	Deerfield et al.	Raytheon Company	ARRAY PROCESSOR FOR DIGITAL COMPUTERS
US4037213	1977-07	Atkins et al.	International Business Machines Corporation	Data processor using a four section instruction format for control of multi-operation functions by a single instruction
US4128880	1978-12	Cray, Jr.	Cray Research, Inc.	Computer vector register processing
US4302818	1981-11	Niemann	Texas Instruments Incorporated	Micro-vector processor
US4306287	1981-12	Huang	Bell Telephone Laboratories, Incorporated	Special address generation arrangement
US4449184	1984-05	Pohlman, III et al.	Intel Corporation	Extended address, single and multiple bit microprocessor
US4463441	1984-07	Kassabou et al.	V M E I "Lenin"	Register arithmetic device
US4463796	1985-06	Omoda et al.		Continuous metal casting method and plant for performing same
US4541046	1985-09	Nagashima et al.	Hitachi, Ltd.	Data processing system including scalar data processor and vector data processor
US4594682	1986-06	Drimak	IBM Corporation	Vector processing
US4636942	1987-01	Chen et al.	Cray Research, Inc.	Computer vector multiprocessing control
US4641275	1987-02	Hatakeyama et al.	Hitachi, Ltd.	Vector processor having pair process mode and single process mode
US4661900	1987-04	Chen et al.	Cray Research, Inc.	Flexible chaining in vector processor with selective use of vector registers as operand and result registers
US4760518	1988-07	Potash et al.	Scientific Computer Systems Corporation	Bi-directional databus system for supporting superposition of vector and scalar operations in a computer
US4760525	1988-07	Webb	The United States of America as represented by the Secretary of the Air Force	Complex arithmetic vector processor for performing control function, scalar operation, and set-up of vector signal processing instruction
US4779192	1988-10	Torii et al.	Hitachi, Ltd.	Vector processor with a synchronously controlled operand fetch circuits
US4780811	1988-10	Aoyama et al.	Hitachi, Ltd.	Vector processing apparatus providing vector and scalar processor synchronization
US4837730	1989-06	Cook et al.	Scientific Computer Systems Corporation	Linking scalar results directly to scalar operation inputs on a bidirectional databus in a computer which superpositions vector and scalar operations
US4875161	1989-10	Lahti	Unisys Corporation	Scientific processor vector file organization
US4888679	1989-12	Fossum et al.	Digital Equipment Corporation	Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements


	Foreign References:			None
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