 |
|
|
|
|
|
 Title: |
US5276833:
Data cache management system with test mode using index registers and CAS disable and posted write disable
[ Derwent Title ]
|
| Country: |
US United States of America
|
| |
| Inventor: |
Auvinen, Stuart T.; Santa Cruz, CA
Nale, William H.; Livermore, CA
|
| Assignee: |
Chips and Technologies, Inc., San Jose, CA
other patents from CHIPS & TECHNOLOGIES, LLC (765535) (approx. 81)
News, Profiles, Stocks and More about this company
|
| Published / Filed: |
1994-01-04
/ 1990-07-02
|
| Application Number: |
US1990000544821
|
| IPC Code: |
Advanced:
G06F 11/22;
G06F 12/08;
G11C 29/52;
Core:
more...
IPC-7:
G06F 11/22;
|
| U.S. Class: |
Current:
711/105;
711/E12.017;
714/718;
714/723;
714/E11.145;
Original:
395/425;
364/DIG.1;
371/021.1;
371/021.6;
395/400;
|
| Field of Search: |
364/200 MS File,900 MS File
395/400,425
371/21.1,21.6
|
| Priority Number: |
| 1990-07-02 |
US1990000544821 |
|
| Abstract: |
A memory controller which can be used with an external tag RAM is disclosed. Existing index registers in the controller serve double duty as buffers for storing tag RAM data during a test mode. Input/output lines for the external tag RAM are coupled to the index registers in addition to being coupled to a comparator for comparison with an external address during normal operation. A buffer is provided so that data from the external address from the CPU can be written through these same tag RAM input/output lines in order to update the tag RAM after a miss. In order to prevent DRAMS from putting data on the memory bus during a cache RAM test, a CAS inhibit signal is provided to the DRAM state machine. Posted writes are also disabled to avoid interference with the address provided to the tag RAM.
|
| Attorney, Agent or Firm: |
Townsend and Townsend Khourie and Crew ;
|
| Primary / Asst. Examiners: |
Dixon, Joseph L.; Nguyen, Hiep T.
|
| INPADOC Legal Status: |
Show legal status actions
|
| Family: |
None
|
First Claim:
Show all 5 claims |
What is claimed is:
1. A memory controller for use with an external tag RAM in a system having a processor coupled to an address bus and a data bus, said system including DRAM memory and cache SRAM memory coupled to a memory data bus coupled to said processor, said memory controller comprising:
- a plurality of tag data input/output lines for coupling to said external tag RAM;
- a plurality of address bus input lines for coupling to said address bus to provide addresses for comparison to addresses in said tag RAM;
- a comparator having first inputs coupled to said tag data input/output lines, second inputs coupled to said address bus input lines and an output for producing a hit/miss signal;
- an index data bus, coupled to said data bus, for providing tag test write data;
- a first multiplexer having first inputs coupled to said index data bus, second inputs coupled to said tag data input/output lines and an output for providing either said tag test write data or tag data from said tag RAM, and a select input for selecting between said first and second inputs;
- an index register having inputs coupled to said output of said first multiplexer for holding either said tag test write data or said tag data;
- a second multiplexer having first inputs coupled to said address bus input lines, second inputs coupled to the outputs of said index register and outputs coupled to said tag data input/output lines and a select input for selecting between said tag test write data and data from said address bus input lines;
- a DRAM state machine having a control input coupled to said comparator output for generating memory cycle timing signals for both said DRAM memory and said cache SRAM memory, including RAS and CAS signals for said DRAM memory only; and
- means for inhibiting said CAS signals during a test access of said cache SRAM memory to isolate said DRAM memory from said memory data bus during said test access.
|
| Background / Summary: |
Show background / summary
|
| Drawing Descriptions: |
Show drawing descriptions
|
| Description: |
Show description
|
| Forward References: |
Show 30 U.S. patent(s) that reference this one
|
