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 Title: |
US5280200:
Pipelined buffer for analog signal and power supply
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Tarng, Min M.; San Jose, CA 95129
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| Assignee: |
None
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| Published / Filed: |
1994-01-18
/ 1992-03-23
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| Application Number: |
US1992000854800
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| IPC Code: |
Advanced:
H01L 27/07;
H01L 27/11;
H01L 27/115;
Core:
more...
IPC-7:
H03K 19/086;
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| U.S. Class: |
Current:
327/312;
257/E27.028;
257/E27.098;
257/E27.103;
326/062;
326/121;
327/316;
Original:
307/446;
307/554;
307/451;
307/494;
307/475;
307/546;
307/548;
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| Field of Search: |
307/554,562,451,494,496,497,296.1,296.8,475,546,548
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| Priority Number: |
| 1990-09-05 |
US1990000579260 |
| 1989-04-10 |
US1989000335584 |
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| Abstract: |
The analog dynamic superbuffer comprises the level shift stage, voltage clamping stage and the dynamic buffer stage. The clamping circuit enables the output buffer having the dynamic driving capability to drive a very large output load with very little static DC bias power consumption.
The TTL power supply is constituted of the stages of TTL power level shift and the analog superbuffer. The huge impact of the power source load is completely blocked by the analog superbuffer.
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| Primary / Asst. Examiners: |
Sikes, William L.; Ouellette, Scott A.
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| Maintenance Status: |
E1 Expired Check current status
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| INPADOC Legal Status: |
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Family Legal Status Report
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| Related Applications: |
| Application Number |
Filed |
Patent |
Pub. Date |
Title |
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| US1990000579260 | 1990-09-05 |
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| US1989000335584 | 1989-04-10 |
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| Parent Case: |
This is a continuation-in-part of Ser. No. 07/579,260 Filed Sep. 5, 1990, now abandoned, which is a continuation in part of Ser. No. 07/335,584, now abandoned.
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| Family: |
Show 2 known family members
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First Claim:
Show all 31 claims |
What I claim is:
1. A circuit for voltage clamping comprising a voltage clamping subcircuit to generate a pair of clamping voltages to clamp an output voltage to be equal to an input voltage, said voltage clamping subcircuit comprising
- a first supply voltage,
- a second supply voltage,
- an input terminal,
- a first output clamping voltage,
- a second output clamping voltage,
- an N-type transistor having a gate and a drain connected together,
- a P-type transistor having a gate and a drain connected together to generating said first output clamping voltage, and having a source connected to a source of said N-type transistor,
- a differential amplifier having a first input from said input terminal and
- a second input from the source of said N-type transistor,
- a first current source connected with said first supply voltage and the drain of said N-type transistor, an output of said differential amplifier being coupled to said first current source to form a feedback loop,
- a second current source being connected with said second supply voltage and the drain of said P-type transistor, said P-type transistor having said drain and a gate connected together to generate said second output clamping voltage.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 12 U.S. patent(s) that reference this one
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