 |
|
|
|
|
|
 Title: |
US5317718:
Data processing system and method with prefetch buffers
[ Derwent Title ]
|
| Country: |
US United States of America
|
| |
| Inventor: |
Jouppi, Norman P.; Palo Alto, CA
|
| Assignee: |
Digital Equipment Corporation, Maynard, MA
other patents from DIGITAL EQUIPMENT CORPORATION (147695) (approx. 2,345)
News, Profiles, Stocks and More about this company
|
| Published / Filed: |
1994-05-31
/ 1993-01-25
|
| Application Number: |
US1993000010446
|
| IPC Code: |
Advanced:
G06F 12/08;
F02B 75/02;
Core:
more...
IPC-7:
G06F 12/08;
|
| ECLA Code: |
G06F12/08B8;
|
| U.S. Class: |
Current:
711/137;
711/122;
711/128;
711/169;
711/E12.057;
Original:
395/425;
364/DIG.1;
364/243.45;
364/244.5;
|
| Field of Search: |
395/400,425
364/200 MS File,900 MS File
|
| Priority Number: |
| 1993-01-25 |
US1993000010446 |
| 1990-03-27 |
US1990000500062 |
|
| Abstract: |
A memory system (10) utilizes miss caching by incorporating a small fully-associative miss cache (42) between a cache (18 or 20) and second-level cache (26). Misses in the cache (18 or 20) that hit in the miss cache have only a one cycle miss penalty, as opposed to a many cycle miss penalty without the miss cache (42). Victim caching is an improvement to miss caching that loads a small, fully associative cache (52) with the victim of a miss and not the requested line. Small victim caches (52) of 1 to 4 entries are even more effective at removing conflict misses than miss caching. Stream buffers (62) prefetch cache lines starting at a cache miss address. The prefetched data is placed in the buffer (62) and not in the cache (18 or 20). Stream buffers (62) are useful in removing capacity and compulsory cache misses, as well as some instruction cache misses. Stream buffers (62) are more effective than previously investigated prefetch techniques when the next slower level in the memory hierarchy is pipelined. An extension to the basic stream buffer, called multi-way stream buffers (62), is useful for prefetching along multiple intertwined data reference streams.
|
| Attorney, Agent or Firm: |
Flehr, Hohbach, Test, Albritton & Herbert ;
|
| Primary / Asst. Examiners: |
Dixon, Joseph L.; Nguyen, Hiep T.
|
| INPADOC Legal Status: |
Show legal status actions
Family Legal Status Report
|
|
|
|
|
|
|
| Parent Case: |
This is a continuation of application Ser. No. 07/500,062, filed Mar. 27, 1990 now abandoned.
|
| Designated Country: |
DE FR GB IT
|
| Family: |
Show 9 known family members
|
First Claim:
Show all 20 claims |
What is claimed is:
1. A data processing system, comprising:
- a first memory for storing information to be supplied to a processor;
- a second memory for storing information to be supplied to said processor through said first memory; and
- a stream buffer connected between said first memory and said second memory, for supplying information from said second memory to said first memory when a miss occurs in said first memory for addressed information at a processor specified address, said stream buffer including prefetch means for retrieving from said second memory, in addition to said information supplied to said first memory, additional information at at least one address successive with respect to said processor specified address and for storing said additional retrieved information;
- said stream buffer having substantially smaller storage than said first memory; and
- said stream buffer including means for storing an address tag corresponding to said information stored in said stream buffer, for comparing said address tag with said processor specified address when a miss occurs in said first memory, and when said address tag matches said processor specified address supplying the corresponding information stored in said stream buffer to said first memory.
|
| Background / Summary: |
Show background / summary
|
| Drawing Descriptions: |
Show drawing descriptions
|
| Description: |
Show description
|
| Forward References: |
Show 114 U.S. patent(s) that reference this one
|
|
|
|
|
|
|
| Foreign References: |
|
| Other Abstract Info: |
DERABS G91-289956
|
| Other References: |
Liu, L., "Increasing Hit Ratios in Second Level Caches and Reducing the Size of Second Level Storage" IBM Technical Disclosure Bulletin: vol. 27, No. 1A, Jun. 1984.
Maytal, B., et al; "Design Considerations for a General-Purpose Microprocessor"; Computer, vol. 22, No. 1, Jan. 1989.
Jouppi, Norman, "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers", Computer Architectur News: vol. 18, No. 2, Jun. 1990.
|
|
 Nominate this for the Gallery...
|
|
