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 Title: |
US5355377:
Auto-selectable self-parity generator
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Venkidu, Arockiyaswamy; Milpitas, CA
Jones, Larry; Palo Alto, CA
Antonopoulos, Nick; San Jose, CA
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| Assignee: |
Tetra Assoc. Inc., San Jose, CA
OnSpec Electronic Inc., Santa Clara, CA
other patents from TETRA ASSOC. INC. (705501) (approx. 1)
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| Published / Filed: |
1994-10-11
/ 1993-11-23
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| Application Number: |
US1993000156075
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| IPC Code: |
Advanced:
G06F 11/10;
Core:
more...
IPC-7:
G06F 11/10;
H03M 13/00;
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| ECLA Code: |
G06F11/10M2D1S;
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| U.S. Class: |
Current:
714/805;
714/E11.047;
Original:
371/051.1;
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| Field of Search: |
371/51.1,19,49.1,49.2,49.3
365/200
364/266.3,267.91
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| Priority Number: |
| 1993-11-23 |
US1993000156075 |
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| Abstract: |
A parity generating circuit that can replace the parity bit DRAM on a 9-bit SIMM. The parity generating circuit includes a parity generating tree which outputs the resulting even parity from the 8 data bits on a read. A 9th data input from another parity generator on the system mother board is compared to the generator tree output when DRAM is written to. If a mismatch occurs, the type of parity generated by the generator tree is opposite to the type of parity that the mother board generates, and the parity tree output must be inverted on subsequent reads. A latch is provided to store the compare result, which also indicates the type of parity required, even or odd, on the particular system the SIMM is installed on. The latch is loaded when the DRAM is written to. The state of the latch is used to output the correct type of parity on a read from DRAM by inverting the output of the parity generating circuit if needed. This eliminates the cost of the 9th DRAM chip on the SIMM, yet allows for parity checking of the data paths on the system board traces and any older 9-bit memory present in the system.
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| Attorney, Agent or Firm: |
Auvinen, Stuart ;
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| Primary / Asst. Examiners: |
Beausoliel, Jr., Robert W.; Elmore, Stephen C.
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| Maintenance Status: |
E2 Expired Check current status
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| INPADOC Legal Status: |
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| Family: |
None
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First Claim:
Show all 17 claims |
We claim:
1. A memory module for installation on a printed circuit mother board, the printed circuit mother board providing an external parity checker, the memory module comprising:
- data memory chips for storing digital data in a plurality of locations within the data memory chips, having data inputs and outputs, control inputs and address inputs;
- a parity generator, responsive to the data outputs, for calculating parity of the digital data;
- a substrate, the substrate being an epoxy-glass printed circuit board substrate, having a length and width adequate for mounting thereon the data memory chips and the parity generator, and for interconnecting the control inputs and address inputs, and for interconnecting the data outputs from the data memory chips to the parity generator;
- terminals on the substrate for providing access to the data inputs and outputs, control inputs and address inputs to enable reading and writing of digital data into and out of the data memory chips;
- a parity output terminal on the substrate for outputting the parity calculated by the parity generator, for transmission to the external parity checker;
- a parity input terminal on the substrate, interconnected to the parity generator, for inputting externally generated parity during writing to locations in the data memory chips;
- parity type determining means, coupled to the parity input terminal and the parity generator, for determining a type of parity required by the external parity checker;
- storage means, coupled to parity determining means, to store the type of parity required by the external parity checker; and
- inverting means, responsive to the storage means, for inverting the parity calculated by the parity generator;
- whereby even or odd parity information will be outputted by the memory module depending upon the type of parity required by the external parity checker.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 7 U.S. patent(s) that reference this one
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