 |
|
|
|
|
|
 Title: |
US5386547:
System and method for exclusive two-level caching
[ Derwent Title ]
>> View Certificate of Correction for this publication
|
| Country: |
US United States of America
|
| |
| Inventor: |
Jouppi, Norman P.; Palo Alto, CA
|
| Assignee: |
Digital Equipment Corporation, Maynard, MA
other patents from DIGITAL EQUIPMENT CORPORATION (147695) (approx. 2,345)
News, Profiles, Stocks and More about this company
|
| Published / Filed: |
1995-01-31
/ 1992-01-21
|
| Application Number: |
US1992000823671
|
| IPC Code: |
Advanced:
G06F 12/08;
Core:
more...
IPC-7:
G06F 12/02;
|
| ECLA Code: |
G06F12/08B22L;
|
| U.S. Class: |
Current:
711/122;
711/E12.043;
Original:
395/425;
364/DIG.1;
364/243.45;
|
| Field of Search: |
395/400,425
364/200 MS File,900 MS File
|
| Priority Number: |
| 1992-01-21 |
US1992000823671 |
|
| Abstract: |
A simple mixed first level cache memory system (50) includes a level 1 cache (52) connected to a processor (54)by read data and write data lines (56) and (58). The level 1 cache (52) is connected to level 2 cache (60) by swap tag lines (62) and (64), swap data lines (66) and (68), multiplexer (70) and swap/read Line (72). The level 2 cache (60) is connected to the next lower level in the memorv hierarchy by write tag and write data lines (74) and (76). The next lower level in the memory hierarchy below the level 2 cache (60) is also connected by a read data line (78) through the multiplexer (70) and the swap/read line (72) to the level 1 cache (52). When processor (54) requires an instruction or data, it puts out an address on lines (80). If the instruction or data is present in the level 1 cache (52), it is supplied to the processor (54) on read data line (56). If the instruction or data is not present in the level 1 cache (52), the processor looks for it in the level 2 cache (60) by putting out the address of the instruction or data on lines (80). If the instruction or data is in the level 2 cache, it is supplied to the processor (54) through the level 1 cache (52) by means of a swap operation on tag swap lines (62) and (64), swap data lines (66) and (68), multiplexer (70) and swap/read data line (72). If the instruction or data is present in neither the level 1 cache (52) nor the level 2 cache (60), the address on lines (80) fetches the instruction or data from successively lower levels in the memory hierarchy as required via read data line (78), multiplexer (70) and swap/read data line (72). The instruction or data is then supplied from the level 1 cache to the processor (54).
|
| Attorney, Agent or Firm: |
Flehr, Hohbach, Test, Albritton & Herbert ;
|
| Primary / Asst. Examiners: |
Dixon, Joseph L.; Nguyen, Hiep T.
|
| Maintenance Status: |
CC Certificate of Correction issued
View Certificate of Correction
|
| INPADOC Legal Status: |
Show legal status actions
|
| Family: |
None
|
First Claim:
Show all 29 claims |
What is claimed is:
1. A cache memory system, which comprises:
- a first-level cache configured to store tags and data associated with the tags,
- a second-level cache configured to store tags and data associated with the tags, said second level cache having a memory capacity at least half as large as that of said first-level cache,
- a next lower-level memory configured to receive tags and store data associated with the tags,
- a multiplexer for receiving said data from said second-level cache and said next lower-level memory,
- said first-level cache and said second-level cache being connected by first swap tag line and first swap data line, said first swap tag line and said first swap data line for transferring discarded tags and data associated with discarded tags from said first-level cache to said second level cache,
- said first-level cache and said second-level cache connected by a second swap data line coupled via said multiplexor, said second swap data line connected to a first input of said multiplexor whose output is coupled to said first-level cache, said second swap data line for transferring data from said second-level cache to said first-level cache,
- said first level cache being connected to read data and write data lines for connection to a processor,
- said second-level cache being connected to write tag and write data lines for connection to said next lower-level memory,
- read data lines connected from the next lower level memory to a second input of said multiplexor for transferring data directly to said first-level cache,
- whereby upon a hit in said second-level cache or said next-lower level memory, said multiplexor transfers data directly into said first level cache while simultaneously said first-level cache writes said discarded tags and data associated with the discarded tags to said second-level cache.
|
| Background / Summary: |
Show background / summary
|
| Drawing Descriptions: |
Show drawing descriptions
|
| Description: |
Show description
|
| Forward References: |
Show 72 U.S. patent(s) that reference this one
|
