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 Title: |
US5444397:
All-CMOS high-impedance output buffer for a bus driven by multiple power-supply voltages
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Wong, Anthony Y.; Saratoga, CA
Kwong, David; Fremont, CA
Yang, Lee; Cupertino, CA
Hsiao, Charles; Fremont, CA
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| Assignee: |
Pericom Semiconductor Corp., San Jose, CA
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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| Published / Filed: |
1995-08-22
/ 1994-10-05
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| Application Number: |
US1994000318238
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| IPC Code: |
Advanced:
H01L 27/02;
H01L 27/118;
H03K 19/00;
H03K 19/003;
H03K 19/0175;
H03K 19/0948;
Core:
more...
IPC-7:
H03K 19/0175;
H03K 19/02;
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| ECLA Code: |
H01L27/02B3B; H01L27/118P; H03K19/003C;
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| U.S. Class: |
Current:
326/081;
257/E27.11;
326/027;
326/058;
327/057;
Original:
326/081;
326/058;
326/027;
327/057;
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| Field of Search: |
326/027,58,81
327/534,537,546
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| Priority Number: |
| 1994-10-05 |
US1994000318238 |
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| Abstract: |
An all-CMOS output buffer drives a bus that can operate at 3 volts and 5 volts. When in a high-impedance state, the output buffer draws little or no current. If the bus is driven to 5 volts by an external device, the high impedance output buffer is in danger of latch-up and distortion of the bus logic level since it only has a 3-volt power supply and does not use a charge pump or an extra 5-volt supply. A biasing circuit couples an N-well that contains p-channel transistors and a driver transistor to the bus driven to 5 volts. Thus the N-well is also driven to 5 volts, the voltage on the bus. The gate of the p-channel driver transistor in the high-impedance output buffer is also coupled to the N-well by another p-channel transistor, raising the gate potential to 5 volts. Thus the gate and body of the p-channel driver transistor is at 5 volts, eliminating reversing current and latch-up problems. A transmission gate isolates the gate of the p-channel driver transistor from the rest of the device's circuitry. The p-channel transistors of the transmission gate, bias circuitry, and driver transistor are located in the N-well, which is biased up to 5 volts only when necessary. Thus during normal operation, the N-well of the driver transistor is at 3 volts, eliminating a performance loss from the body effect. A logic gate increases the well bias and isolates the driver's gate only when necessary, when the bus is high and driven by a 5-volt device, and the output buffer is in high-impedance.
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| Attorney, Agent or Firm: |
Auvinen, Stuart T. ;
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| Primary / Asst. Examiners: |
Hudspeth, David R.; Sanders, Andrew
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| INPADOC Legal Status: |
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Family Legal Status Report
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| Designated Country: |
DE FR GB IT
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| Family: |
Show 7 known family members
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First Claim:
Show all 16 claims |
We claim:
1. An output buffer having a high-impedance state, the output buffer coupled to a first power supply producing a first power supply voltage, the output buffer comprising:
- an output coupled to a bus, the bus having a low logic state and a high logic state, the high logic state corresponding to a voltage substantially at the first power supply voltage when the output buffer is driving the bus, the high logic state corresponding to a voltage substantially at a second power supply voltage higher than the first power supply voltage when the output buffer is not driving the bus and the output buffer is in the high-impedance state;
- a p-channel driver transistor, having a source coupled to the first power supply and a drain coupled to the output, the p-channel driver transistor for pulling the output high to the first power supply voltage, the p-channel driver transistor being in an N-well;
- a bias circuit comprising
- well bias means, coupled to the first power supply and coupled to the output, for biasing the N-well, the well bias means coupling the N-well to the first power supply when the output buffer is driving the bus, the well bias means coupling the output to the N-well when the output buffer is not driving the bus and the bus is substantially at the second power supply voltage higher than the first power supply voltage; and
- isolation engaging means, coupled to the well bias means, for signaling when the N-well is to be isolated from the first power supply and coupled to the output, the isolation engaging means coupled to the output, the isolation engaging means signaling that the N-well is to be isolated from the first power supply when the bus is substantially at the second power supply voltage;
- wherein the isolation engaging means comprises:
- isolation detect means, receiving an indication that the output buffer is not driving the bus, the isolation detect means also receiving an indication that the bus is in the high logic state, for indicating when the N-well is to be isolated from the first power supply; and
- signal inversion means, coupled to the isolation detect means, for signaling that the N-well is to be isolated from the first power supply,
- whereby the N-well containing the p-channel driver transistor is biased to substantially the second power supply voltage when the bus is substantially at the second power supply voltage.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 52 U.S. patent(s) that reference this one
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