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 Title: |
US5479363:
Programmable digital signal processor using switchable unit-delays for optimal hardware allocation
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Willson, Jr., Alan N.; Pasadena, CA
Khoo, Kei Y.; Portland, OR
Kwentus, Alan; Torrance, CA
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| Assignee: |
The Regents of the University of California, Oakland, CA
other patents from UNIVERSITY OF CALIFORNIA, THE REGENTS OF (599425) (approx. 4,840)
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| Published / Filed: |
1995-12-26
/ 1993-04-30
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| Application Number: |
US1993000055975
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| IPC Code: |
Advanced:
H03H 17/02;
Core:
more...
IPC-7:
G06F 15/31;
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| ECLA Code: |
H03H17/02H;
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| U.S. Class: |
Current:
708/319;
Original:
364/724.16;
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| Field of Search: |
364/724.16,724.13,724.01,724.1
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| Priority Number: |
| 1993-04-30 |
US1993000055975 |
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| Abstract: |
A novel switchable unit-delay has been developed for the efficient implementation of programmable digital finite impulse response filters and correlators. A p-tap consisting of this novel switchable unit-delay and a two-non-zero-digit partial product generator and adder have been implemented. The combination of several p-taps, made possible by the switchable unit-delay, allows for the efficient implementation of coefficients with more than two non-zero digits. In a straightforward implementation of a programmable finite impulse response filter, many tap "multipliers" would significantly waste valuable computational resources since all filter taps would need to accommodate "difficult" coefficient values (i.e., many non-zero digits), while for any specific transfer function, most filter taps would not require such extreme capabilities. The switchable unit-delay not only allows the programing of the number of taps and the specific tap-coefficient values, it provides the capability for programing the optimal allocation of hardware resources to each filter tap.
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| Attorney, Agent or Firm: |
Loeb and Loeb ;
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| Primary / Asst. Examiners: |
Mai, Tan V.;
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| Maintenance Status: |
CC Certificate of Correction issued
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| INPADOC Legal Status: |
Show legal status actions
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| Family: |
None
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First Claim:
Show all 10 claims |
We claim:
1. A first digital filter tap element having a first predetermined number of digits for part of a filter having a plurality of such tap elements for digitally filtering an input digital signal according to an algorithm based upon a first filter coefficient having a second predetermined number of digits, the first tap element comprising:
- a coefficient multiplier having the first number of digits for multiplying at least a part of the input with a coefficient to form a product;
- an adder responsive to the product of the multiplier and a second input providing as an output the sum of the product and the second input;
- a delay element providing both a delayed and an undelayed signal coupled to one of the inputs to the multiplier or the output of the adder; and
- means for selecting between the delayed and undelayed signal so that where the second number is greater than the first number, a second such tap element is combined with the first element to multiply the digital signal with the coefficient having the second number of digits.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 12 U.S. patent(s) that reference this one
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| Foreign References: |
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| Other Abstract Info: |
DERABS G96-057993
DERG96-057993
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| Other References: |
C. Golla, F. Nava, F. Cavallotti, A. Cremonesi, P. Piacentini, G. Casagrande, and G. Campardo, "A 30M samples/s programmable filter processor," Proc. IEEE Int. Solid-State Circuits Conf., pp. 116-117, 1990.
M. Hatamian and S. K. Rao, "A 100MHz 40-tap programmable FIR filter chip," Proc. Int. Symp. Circuits and Systems, vol. 4, pp. 3053-3056, May 1-3, 1990.
J. B. Evans, Y. C. Lim, and B. Liu, "A high speed programmable digital FIR filter," Proc. ICASSP-90, vol. 2, pp. 969-971, Apr. 3-6, 1990.
H. Samueli, "An Improved Search Algorithm for the Design of Multiplierless FIR Filters with Powers-of-Two Coefficients," IEEE Trans. Circuits Syst., vol. CAS-36, No. 7, pp. 1044-1047, Jul. 1989.
(4 pages)
Cited by 7 patents
J. Laskowski, "A Silicon Compiler for Liner-Phase FIR Digital Filters," pp. 1-23 and 58-59, University of California, Los Angeles (Master's thesis), 1991.
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