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 Title: |
US5489904:
Analog current mode analog/digital converter
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Hadidi, Khayrollah; Tokyo, Japan
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| Assignee: |
The Regents of the University of California, Oakland, CA
other patents from UNIVERSITY OF CALIFORNIA, THE REGENTS OF (599425) (approx. 4,840)
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| Published / Filed: |
1996-02-06
/ 1993-09-28
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| Application Number: |
US1993000127761
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| IPC Code: |
Advanced:
H03M 1/16;
H03M 1/74;
H03M 1/76;
Core:
H03M 1/14;
more...
IPC-7:
H03M 1/14;
H03M 1/68;
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| ECLA Code: |
H03M1/16S;
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| U.S. Class: |
Current:
341/156;
341/136;
341/145;
Original:
341/156;
341/136;
341/145;
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| Field of Search: |
341/133,136,145,156
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| Government Interest: |
This invention was made with support under NASA Grant No. NAG 2-360 and NSF Grant No. MIP 9014127. Accordingly, the U.S. Government may have certain rights in the invention.
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| Priority Number: |
| 1993-09-28 |
US1993000127761 |
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| Abstract: |
An improved subranging or comparator circuit is provided for an analog-to-digital converter. As a subranging circuit, the circuit produces a residual signal representing the difference between an analog input signal and an analog of a digital representation. This is achieved by subdividing the digital representation into two or more parts and subtracting from the analog input signal analogs of each of the individual digital portions.
In another aspect of the present invention, the subranging circuit comprises two sets of differential input pairs in which the transconductance of one differential input pair is scaled relative to the transconductance of the other differential input pair. As a consequence, the same resistor string may be used for two different digital-to-analog converters of the subranging circuit.
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| Attorney, Agent or Firm: |
Loeb and Loeb ;
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| Primary / Asst. Examiners: |
Williams, Howard L.;
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| Maintenance Status: |
E2 Expired Check current status
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| INPADOC Legal Status: |
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| Family: |
None
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First Claim:
Show all 32 claims |
I claim:
1. An analog to digital converter for converting an analog input voltage signal to a digital representation, comprising:
- a first digital to analog converter for converting a first plurality of bits to a first analog voltage signal;
- a first pair of differential input transistors having a pair of inputs coupled to the first analog voltage signal and the analog input voltage signal to produce a first analog difference signal;
- a second digital to analog converter for converting a second plurality of bits to a second analog voltage signal; and
- a second pair of differential input transistors having a pair of inputs coupled to the second analog voltage signal and a reference voltage signal to produce a second analog difference signal;
- a coupler circuit for coupling the first and second analog difference signals to produce an analog residual signal; and
- a residual converter for converting the residual analog signal to a digital representation.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 34 U.S. patent(s) that reference this one
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| Foreign References: |
None
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| Other Abstract Info: |
DERABS G1996-115760
DERABS G1996-115760
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| Other References: |
G. C. Temes, "High Accuracy Pipeline A/D Convertor Configuration," Electronic Letters, vol. 21, No. 17, pp. 762-763, Aug., 1985.
(2 pages)
Fig. 3.1 The Pipeline A/D Converter, prior to the filing date of the present application.
Fig. 3.5 Block diagram of a general pipelined A/D converter, prior to the filing date of the present application.
Kh. Hadidi et al., "An 8-b 1.3-MHz Successive-Approximation A/D Converter," IEEE Journal of Solid-State Circuits, vol. 25, No. 3, Jun. 1990.
Kh. Hadidi et al., "A New Method of Implementing DACs in CMOS Subranging Stages," University of California, Los Angeles.
Kh. Hadidi et al., "Fast Successive-Approximation A/D Converters," University of California, Los Angeles, prior to filing date of the present application.
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