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 Title: |
US5574401:
Large common mode input range CMOS amplifier
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Spitalny, Paul A.; Everett, WA
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| Assignee: |
Analog Devices, Inc., Norwood, MA
other patents from ANALOG DEVICES, INC. (28725) (approx. 876)
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| Published / Filed: |
1996-11-12
/ 1995-06-02
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| Application Number: |
US1995000460084
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| IPC Code: |
Advanced:
H03F 3/30;
H03F 3/45;
Core:
more...
IPC-7:
H03F 3/45;
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| ECLA Code: |
H03F3/30B6A2; H03F3/30B6A; H03F3/45B3B2; H03F3/45S1B3;
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| U.S. Class: |
Current:
330/253;
330/261;
Original:
330/253;
330/261;
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| Field of Search: |
330/253,254,257,258,261
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| Priority Number: |
| 1995-06-02 |
US1995000460084 |
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| Abstract: |
A CMOS amplifier input stage including an NMOS differential pair connected in parallel with a PMOS differential pair. Each pair is connected to a tail-current transistor of the same type, and the combined circuits are coupled between positive and negative supply rails. The gates of the tail-current transistors receive the amplifier input signal to provide adaptive biasing of the differential pairs, resulting in a total combined transconductance for both differential pairs which is at least approximately constant with changes in input signal level, thereby enlarging the available common-mode input signal range of the amplifier.
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| Attorney, Agent or Firm: |
Parmelee, Bollinger & Bramblett ;
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| Primary / Asst. Examiners: |
Mottola, Steven;
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| INPADOC Legal Status: |
Show legal status actions
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| Family: |
None
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First Claim:
Show all 11 claims |
What is claimed is:
1. An amplifier comprising:
- a differential pair of NMOS transistors;
- an NMOS transistor connected to said NMOS differential pair to conduct the tail current thereof;
- a differential pair of PMOS transistors;
- a PMOS transistor connected to said PMOS differential pair to conduct the tail current thereof;
- means connecting said NMOS differential pair together with said tail current NMOS transistor between two supply rails;
- means connecting said PMOS differential pair together with said tail current PMOS transistor between said supply rails;
- first and second input terminals to provide an input signal to said NMOS and PMOS differential pairs;
- means responsive to the input signal for controlling said tail-current NMOS and PMOS transistors to effect adaptive biasing of said transistors; and
- means to combine the outputs of said differential pairs to produce a composite output signal.
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| Background / Summary: |
Show background / summary
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| Drawing Descriptions: |
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| Description: |
Show description
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| Forward References: |
Show 16 U.S. patent(s) that reference this one
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| Foreign References: |
None
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| Other Abstract Info: |
DERABS G1996-518009
DERABS G1996-518009
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| Other References: |
"A Rail-to-Rail CMOS Op Amp", J. N. Babanezhad, IEEE Journal of Solid State Circuits, Dec. 1988, vol. 23, No. 6 pp. 1414-1417.
(4 pages)
Cited by 4 patents
"A Compact Power-Efficient 3V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Libraries", R. Hogervorst et al, IEEE Journal of Solid State Circuits, Dec. 1994, vol. 29, No. 12 pp. 1505-1513.
(9 pages)
Cited by 6 patents
[ISI abstract]
"Biasing Circuit for High Input Swing Operational Amplifiers" J. F. Duque-Carillo et al, IEEE Journal of Solid State Circuits Feb. 1995, vol. 30, No. 2, pp. 156-159.
(4 pages)
[ISI abstract]
"Constant Transconductance CMOS Amplifier Input Stage With Rail-to-Rail Common Mode Input Range", K. Nagaraj, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, May 1995, vol. 42, No. 5 pp. 366-368.
(3 pages)
[ISI abstract]
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