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 Title: |
US5602882:
Digital jitter attenuator using selection of multi-phase clocks and auto-centering elastic buffer
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Co, Ramon S.; Trabuco Canyon, CA
Lee, Lance K.; Milpitas, CA
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| Assignee: |
Pericom Semiconductor Corp., San Jose, CA
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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| Published / Filed: |
1997-02-11
/ 1996-01-19
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| Application Number: |
US1996000588902
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| IPC Code: |
Advanced:
H04J 3/06;
H04L 12/42;
H04L 7/033;
Core:
more...
IPC-7:
H04L 7/00;
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| ECLA Code: |
H04J3/06B4; H04L12/42S;
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| U.S. Class: |
Current:
375/372;
370/518;
375/373;
Original:
375/372;
375/373;
370/518;
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| Field of Search: |
375/372,373,374,371
370/105.3
327/158,149,144,151
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| Priority Number: |
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| Abstract: |
A jitter attenuator receives data and a receive clock extracted from an input data stream. A transmit clock is generated for retransmitting the data. The transmit clock has less jitter than the receive clock but has the same average frequency. An elastic buffer or FIFO is necessary to buffer the data. The receive clock is divided into a series of write clocks for writing data into the elastic buffer, and the transmit clock is also divided into a series of read clocks for reading data from the elastic buffer. A series of multi-phase clocks is used to generate the transmit clock. The multi-phase clocks all have the same frequency but are offset in phase from one another. A phase selector, under control of a counter, selects one of the multi-phase clocks to be the transmit clock. The counter is incremented or decremented by a phase comparator. The phase comparator compares the phase of one of the write clocks to the phase of one of the read clocks. The counter is incremented when the phase of the write clock lags the read clock, selecting a multi-phase clock with a more retarded phase, but the counter is decremented when the write clock leads the read clock, selecting a multi-phase clock with a more advanced phase. Thus the phase of the transmit clock is adjusted by the phase comparison of the write and read clocks for the elastic buffer. The elastic buffer is forced to half-full by comparing a write and read clock that are separated by half the capacity of the buffer. The phase, rather than the frequency, is adjusted, eliminating the feedback to an external VCO, allowing the jitter attenuator to be integrated on a single silicon substrate.
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| Attorney, Agent or Firm: |
Auvinen, Stuart T. ;
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| Primary / Asst. Examiners: |
Chin, Stephen; Ghebretinsae, T.
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| INPADOC Legal Status: |
None
Family Legal Status Report
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| Parent Case: |
RELATED APPLICATION
This application is a continuation of Ser. No. 08/259,910 filed Jun. 15, 1994, now U.S. Pat. No. 5,502,750.
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| Family: |
Show 2 known family members
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First Claim:
Show all 13 claims |
We claim:
1. A method of attenuating jitter from a first clock by buffering and re-transmitting input data with a second clock, the second clock having less jitter than the first clock, the method comprising:
- receiving the first clock and generating a plurality of write clocks by dividing the first clock, the write clocks having a lower frequency than the first clock, the first clock having a frequency that is a multiple of the frequency of the write clocks;
- receiving into an elastic buffer the input data at the rate of the first clock and providing from the elastic buffer the input data for re-transmission at the rate of the second clock;
- receiving the second clock and generating a plurality of read clocks by dividing the second clock, the read clocks having a lower frequency than the second clock, the second clock having a frequency that is a multiple of the frequency of the read clocks;
- determining the difference in phase between at least one of the plurality of write clocks and at least one of the plurality of read clocks;
- generating a plurality of multi-phase clocks for generating the second clock; and
- receiving the plurality of multi-phase clocks and adjusting the phase of the second clock by selecting a clock in the plurality of multi-phase clocks for generating the second clock in response to the difference in phase between at least one of the plurality of write clocks and at least one of the plurality of read clocks,
whereby jitter in the first clock is attenuated in the second clock.
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| Background / Summary: |
Show background / summary
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| Drawing Descriptions: |
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| Description: |
Show description
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| Forward References: |
Show 26 U.S. patent(s) that reference this one
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