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 Title: |
US5629840:
High powered die with bus bars
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Hamburgen, William R.; Palo Alto, CA
Fitch, John S.; Newark, CA
Jouppi, Norman P.; Palo Alto, CA
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| Assignee: |
Digital Equipment Corporation, Maynard, MA
other patents from DIGITAL EQUIPMENT CORPORATION (147695) (approx. 2,345)
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| Published / Filed: |
1997-05-13
/ 1994-03-28
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| Application Number: |
US1994000218877
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| IPC Code: |
Advanced:
H01L 23/427;
Core:
H01L 23/34;
IPC-7:
H01L 23/02;
H01L 23/48;
H05K 7/02;
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| ECLA Code: |
H01L23/427;
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| U.S. Class: |
Current:
361/820;
174/561;
257/678;
257/691;
257/E23.088;
361/761;
361/775;
Original:
361/820;
174/052.4;
257/678;
257/691;
361/761;
361/775;
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| Field of Search: |
174/52.1,52.2,52.3,52.4
257/666,668,659,692,678,691,693,695,700,734,735,736,758,759,760
361/760-764,772,775,777,779,792
439/068,70,71,72
437/207-209
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| Priority Number: |
| 1994-03-28 |
US1994000218877 |
| 1992-05-15 |
US1992000883544 |
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| Abstract: |
Power bus bars are provided for a semiconductor die. Power bus bars are thick electrical conductors that extend the length of the die in an electrically isolated array of stripes. The electrical stripes are divided into two or more interdigitated groups, each group connected to a power supply, or connected to a ground supply. This arrangement of alternate power and ground stripes minimizes inductance and resistance, and brings power and ground close to every transistor in the semiconductor die with minimized voltage variations.
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| Attorney, Agent or Firm: |
Maloney, Denis G. ;
Fisher, Arthur W. ;
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| Primary / Asst. Examiners: |
Picard, Leo P.; Sparks, Donald A.
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| INPADOC Legal Status: |
Show legal status actions
Family Legal Status Report
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| Parent Case: |
This application is a continuation of application Ser. No. 07/883,544, filed May 15, 1992 now abandoned.
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| Family: |
Show 2 known family members
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First Claim:
Show all 3 claims |
We claim:
1. A high powered die for use with a die package of the type which includes a housing with a central cavity forming an opening on a first side of said housing, said central cavity extending toward a second side of said housing where said high powered die is positioned, said die package further includes bond shelf means accessible to said high powered die through said central cavity for distributing signals and separate bond shelf means for distributing power and ground to said high powered die through bond wires coupled to said high powered die, said high powered die comprising:
- semiconductor chip circuitry located on one or more surfaces of said high powered die, including at least one of said high powered die surfaces usable for power and ground distribution;
- a plurality of discrete electrically isolated bus bars positioned on said one of said die surfaces for power and ground distribution, said plurality of bus bars extending from a first side of said high powered die to a second side of said high powered die, said plurality of discrete electrically isolated bus bars grouped into a first portion of said plurality of discrete electrically isolated bus bars, each having at least one ground connection to said die, and a second portion of said plurality of discrete electrically isolated bus bars, each having at least one power connection to said die, said first and second portions of said plurality of discrete electrically isolated bus bars being coupled at both said first and at said second side of said high powered die to said bond wires of said die package.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 4 U.S. patent(s) that reference this one
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| Foreign References: |
Buy
PDF |
Publication |
Date |
IPC Code |
Assignee |
Title |
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JP03060050
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1991-03 |
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JP03222442
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1991-10 |
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| Other Abstract Info: |
CHEMABS 126(08)112058B
DERABS G97-041984
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| Other References: |
Satch, et al., "A 209K Transistor ELL Gate Array With Ram", IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989.
Fitch, John S. et al; "Microchannel Wafer Cooling Chuck", Ser. No. 07/722,891, Filed Jun. 28, 1991.
Hamburgen, William R. et al, "Fixture and Method for Attaching Components", Ser. No. 07/722,972, Filed Jun. 28, 1991.
Hamburgen, William; "Die Attach Structure and Method", Ser. No. 07/417,730; Filed Oct. 5, 1989.
Hamburgen, William; "Die Attach Structure and Method", Ser. No. 07/628,944, Filed Dec. 14, 1990.
Hamburgen, William; "Hollow Chip Package and Method of Manufacturing", Ser. No. 07/725,376, Filed Jun. 27, 1991.
Hamburgen, William; "Semiconductor Package and Method of Wraparound Metalization", Ser. No. 07/542,179, Filed Jun. 22, 1990.
Hamburgen, William; "Int egrated Circuit Test Fixture and Method", Ser. No 07/546,523, Filed Jun. 29, 1990.
Hamburgen, William; "Gentle Package Extraction Tool and Method", Ser. No. 07/722,656, Filed Jun. 28, 1991.
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