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 Title: |
US5689679:
Memory system and method for selective multi-level caching using a cache level code
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Jouppi, Norman Paul; Palo Alto, CA
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| Assignee: |
Digital Equipment Corporation, Maynard, MA
other patents from DIGITAL EQUIPMENT CORPORATION (147695) (approx. 2,345)
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| Published / Filed: |
1997-11-18
/ 1996-03-05
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| Application Number: |
US1996000610901
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| IPC Code: |
Advanced:
G06F 12/08;
G06F 12/10;
Core:
more...
IPC-7:
G06F 12/08;
G06F 13/00;
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| ECLA Code: |
G06F12/08B22L;
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| U.S. Class: |
Current:
711/122;
711/003;
711/139;
711/E12.043;
Original:
395/449;
395/466;
395/403;
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| Field of Search: |
395/444,446,449,465,466,471,472,473,483,403,445
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| Priority Number: |
| 1996-03-05 |
US1996000610901 |
| 1993-04-28 |
US1993000055232 |
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| Abstract: |
A selective multilevel caching method and system including a main memory and a plurality of cache memories are disclosed. The main memory and cache memories are arranged in a multilevel hierarchy: the main memory is at the lowest hierarchical level; the cache memory that is coupled directly to the central processing unit (CPU) is at the highest hierarchical level; and the remaining cache memories are coupled in the hierarchy at intermediate hierarchical levels therebetween. Each hierarchical level contains cache logic as well as a cache memory. Each cache logic responds to a cache level code that is associated with an address specified in each CPU read or write data request. The cache level code specifies the highest hierarchical level at which data associated with the data request may be written. Each cache logic uses the cache level code to determine if data will be written to the cache memory at the same hierarchical level as that cache logic. Each CPU write request further includes a cache control code. The cache control code indicates whether each cache level is designated as a write-allocate cache level. Each cache logic responds also to the cache control code to further determine if data will be written to the cache memory at the same hierarchical level as that cache logic.
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| Attorney, Agent or Firm: |
Rodriguez, Michael A. ;
Thompson, James F. ;
Johnston, A. Sidney ;
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| Primary / Asst. Examiners: |
Gossage, Glenn;
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| INPADOC Legal Status: |
Show legal status actions
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| Parent Case: |
This application is a continuation of application Ser. No. 08/055,232, filed Apr. 28, 1993, now abandoned.
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| Family: |
None
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First Claim:
Show all 26 claims |
What is claimed is:
1. A memory system for coupling to a central processor, which issues a data request having a specified address to be accessed, the memory system comprising;
- a main memory;
- cache levels coupled between the main memory and the central processor in a multilevel hierarchy, each of the cache levels having a cache memory;
- means, coupled to the processor, for identifying a cache level code associated with the data request, the cache level code indicating a hierarchical level in the multilevel hierarchy; and
- means for determining from the cache level code whether or not data associated with the specified address can be written to the cache memory at each of the cache levels.
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| Background / Summary: |
Show background / summary
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| Drawing Descriptions: |
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| Description: |
Show description
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| Forward References: |
Show 43 U.S. patent(s) that reference this one
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| Foreign References: |
None
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| Other Abstract Info: |
DERABS G98-008310
DERG98-008310
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| Other References: |
Smith, A.J., "Cache Memories", Computing Surveys, vol. 14, No. 3, pp. 473-530 (Sep. 1982).
(58 pages)
Cited by 83 patents
Digital Technical Journal, NVAX-microprocessor VAX Systems, vol. 4 No. 3, Summer 1992, Digital Equipment Corporation, pp. 62-63.
Digital Technical Journal, Alpha AXP Architecture and Systems, vol. 4 No. 4, Special Issue 1992, Digital Equipment Corporation, pp. 66-70 and 100-105.
Computer Architecture A Quantitative Approach 2d Ed. John 1. Hennessy & David Patterson, pp. 461-465.
Computer Programming and Architecture The VAX, Levy & Eckhouse, Jr., pp. 340-343 (Multilevel Caches), 1989.
Digital Technical Journal, VAX-based Systems, No. 7, Aug. 1988, Digital Equipment Corporation, pp. 28-29, 35-38, 41-42, 99.
Digital Technical Journal, Vax 9000 Series, vol. 2 No. 4, Fall 1990, Digital Equipment Corporation, pp. 16, 23.
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