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Title: US5694603: Computer memory product with preemptive multithreading software
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Country: US United States of America

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23 pages

Inventor: Reiffin, Martin G.; Danville, CA 94526

Assignee: None

Published / Filed: 1997-12-02 / 1990-03-20

Application Number: US1990000496282

IPC Code: Advanced: G06F 9/45; G06F 9/48;
IPC-7: G06F 9/46;

ECLA Code: G06F9/48C2T; G06F8/48; G06F9/48C2; G06F9/48C4;

U.S. Class: Current: 718/107;
Original: 395/677;

Field of Search: 395/800,375,650,677,678

Priority Number:
1990-03-20  US1990000496282
1982-09-28  US1982000425612
1985-04-03  US1985000719507

Abstract:     A multithreading computer system for the preemptive asynchronous concurrent execution of a plurality of instruction threads of a multithreaded application program. As an illustrative example of one of the many uses of the invention, the disclosed application program comprises a compiler thread and an editor thread. The compiler processes the source code while the programmer edits the source code at the keyboard. An interrupt sevice routine repeatedly activates the editor thread to provide a preemptive asynchronous editing process for either entry of new source code or modification of the previously entered code, while the compiler thread concurrently processes the source code during the time intervals between keystrokes. The interrupt service routine may be activated either by a keyboard interrupt or periodically by a clock at predetermined time intervals.

Primary / Asst. Examiners: Ellis, Richard L.;

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Related Applications:
Application Number Filed Patent Pub. Date  Title
US1982000425612 1982-09-28       
US1985000719507 1985-04-03       

Parent Case:

    This application is a continuation of my prior applications Ser. No. 06/425,612, filed Sep. 28, 1982, and Ser. No. 06/719,507, filed Apr. 3, 1985, both prior applications allowed but now abandoned and both originally titled "Computer System with Real-Time Compilation". The Detailed Description and FIGS. 1 to 6 of the drawings of the present application are intended to be identical to those of said prior applications. Therefore the present invention is entitled to an effective filing date of Sep. 28, 1982.

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First Claim:
Show all 41 claims
I claim:     1. A computer-readable disk memory having a surface formed with a plurality of binary patterns constituting a multithreaded application program executable by a desktop computer having a central microprocessor, a memory, means for loading said application program into a defined address space of said memory, and a clock-driven periodically-activated interrupt operation providing a plurality of series of spaced timeslices with the timeslices of each series interleaved with the timeslices of at least one other series, said multithreaded program comprising
  • a plurality of sets of instructions with each set executable by said microprocessor to provide a respective thread of execution and with each thread having a respective task to perform,
  • a first of said sets of instructions executable to provide a first thread of execution having control of the central microprocessor during each successive timeslice of a first series of timeslices with successive portions of the task of said first thread performed during respective successive timeslices of said first series,
  • said first thread of execution being periodically preempted in response to activations of said interrupt operation at predetermined fixed time intervals at a fixed frequency in the range of about every ten to thirty milliseconds so as to provide a preemption at each termination of a timeslice of said first series by said clock activation of said interrupt operation, and
  • a second of said sets of instructions executable to provide a second thread of execution and responsive to said periodic preemptions to acquire control of the central microprocessor during successive timeslices of a second series of timeslices with successive portions of the task of said second thread performed during respective successive timeslices of said second series,
  • whereby a preemptive multithreading mode of operation is provided for the concurrent execution of a plurality of instruction threads of the same program with each thread executing successive incremental portions of its task during successive timeslices of a respective series of spaced timeslices and with the successive executed task portions of each thread interleaved with the successive executed task portions of at least one other thread so as to provide concurrent execution of a plurality of threads of the same program,
  • each of said threads having direct access to said program memory address space so as to provide fast efficient preemption of one thread by another thread and switching of control of the central microprocessor back and forth among the threads at a rate so rapid that the threads execute effectively simultaneously,
  • thereby enabling a single microprocessor to simulate the parallel processing of a large complex mainframe computer having multiple central processing units.

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Description: Show description

Forward References: Show 53 U.S. patent(s) that reference this one

U.S. References: Go to Result Set: All U.S. references   |  Forward references (53)   |   Backward references (8)   |   Citation Link

Patent  Pub.Date  Inventor Assignee   Title
Get PDF - 49pp US4084228  1978-04 Dufond et al.  Compagnie Honeywell Bull Process management structures and hardware/firmware control
Get PDF - 10pp US4383307  1983-05 Gibson, III  Software Concepts, Inc. Spelling error detector apparatus and methods
Get PDF - 13pp US4513391  1985-04 Maddock  International Business Machines Corporation Text processing apparatus with two-stage formatting of text
Get PDF - 9pp US4671684  1987-06 Kojima et al.  Brother Kogyo Kabushiki Kaisha Electronic typewriter with selectively deactuatable spelling checking apparatus
Get PDF - 40pp US4724285  1988-02 Lefler et al.  Digitext, Inc. Stenographic translation system
Get PDF - 15pp US4773009  1988-09 Kucera et al.  Houghton Mifflin Company Method and apparatus for text analysis
Get PDF - 25pp US4887212  1989-12 Zamora et al.  International Business Machines Corporation Parser for natural language text
Foreign References: None

Other Abstract Info: DERABS G84-109561

Other References:
  • Hiromoto, Robert, Parallel-processing a large scientific problem, AFIPS Press. 1981, pp. 235-237.
  • Ousterhout, John K., Scheduling techniques for Concurrent Systems, IEEE, 1982, pp. 22-30.
  • Andrews, Gregory R., Synchronizing Resources, ACM Transactions on Programming Languages and Systems, vol. 3, No. 4, Oct. 1981, pp. 405-430. (26 pages) Cited by 2 patents
  • Collin, A. J. T., The Implementation of STAB-1, Software--Practice and Experience, vol. 2, 1972, pp. 137-142.
  • Artym, Richard, The STAB Multiprocessing Environment for CYBA-M, Software--Practice and Experience, vol. 12, 1982, pp. 323-329. (7 pages) Cited by 2 patents
  • Treleaven et al., Combining Data Flow and Control Flow Computing, The Computer Journal, vol. 25, No. 2, 1982, pp. 207-217. (11 pages) Cited by 4 patents
  • Duffie, C. A. III, Task Scheduling Algorithm for a Teleprocessing Communications Controller, , IBM Technical Disclosure Bulletin, vol. 16, No. 10, Marcy 1974, pp. 3349-3352.
  • Hoare, C. A. R., Towards a Theory of Parallel Programming, Operating Systems Techniques, Proceedings of a Seminar held at Queen's University, Belfast, 1972, Aademic Press, 1972, pp. 61-71.
  • Cheriton, David Ross, Multi-Process Structuring and the Thoath Operating System, Doctoral Thesis, University of Waterloo, 1978.
  • Redell et al., Pilot: An Operating System for a Personal Computer, Communications of the ACM, Feb. 1980, vol. 23, No. 2, pp. 81-92. (12 pages) Cited by 2 patents
  • Lampson et al., Experience with Processes and Monitors in Mesa, Communications of the ACM, Feb. 1980, vol. 23, No. 2, pp. 105-117. (13 pages) Cited by 5 patents
  • Hughes, Lawrence, E., "System Programming Under CP/M-80," 1983, pp. 109-112 and 127-138.

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