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Title: US5694604: Preemptive multithreading computer system with clock activated interrupt
[ Derwent Title ]

Country: US United States of America

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20 pages

 
Inventor: Reiffin, Martin G.; Danville, CA 94506

Assignee: None

Published / Filed: 1997-12-02 / 1994-03-25

Application Number: US1994000217669
IPC Code: Advanced: G06F 9/48;
Core: G06F 9/46;
IPC-7: G06F 9/46;

ECLA Code: G06F9/48C2; G06F9/48C2T;

U.S. Class: Current: 718/107;
Original: 395/677;

Field of Search: 395/375,650,677,678

Priority Number:
1994-03-25  US1994000217669
1990-03-20  US1990000496282
1982-09-28  US1982000425612
1985-04-03  US1985000719507

Abstract:     A multithreading computer system provides concurrent asynchronous preemptive time-sliced execution of a plurality of threads of instructions located within the same software program. A clock or timer periodically activates the interrupt operation of the central processor. Each interrupt preempts an executing thread after the thread has executed for a brief timeslice during which the thread may have performed only a portion of its task. Control of the processor is thereby taken away from the preempted thread, and control then passes to an interrupt service routine which then passes control to another thread to invoke the latter for execution during the next timeslice. Control is thereafter returned to the preempted thread to enable the latter to resume execution at the point where it was previously interrupted. Control of the processor is thus transferred repeatedly back and forth between the threads so rapidly that the threads are run substantially simultaneously. The threads may thus execute incrementally and piecewise with their successive task portions executed alternately in a mutually interleaved relation and with each thread executed during its respective series of spaced timeslices interleaved with the timeslices of at least one other thread.

Primary / Asst. Examiners: Ellis, Richard L.;

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Related Applications:
Application Number Filed Patent Pub. Date  Title
US1990000496282 1990-03-20       
US1982000425612 1982-09-28       
US1985000719507 1985-04-03       


       
Parent Case:

PRIOR APPLICATIONS
    This application is a continuation of my prior copending application Ser. No. 07/496,282 filed Mar. 20, 1990 which application was in turn a continuation of my prior applications Ser. No. 06/425,612 filed Sep. 28, 1982 and abandoned Apr. 5, 1990, and Ser. No. 06/719,507 filed Apr. 3, 1985 and abandoned Jun. 8, 1991. The disclosed structure and operation of the present application as filed are identical to those of said three prior applications and support the claims of the present application which is therefore entitled to an effective filing date of Sep. 28, 1982.

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First Claim:
Show all 36 claims		 I claim:     1. A method of preemptive multithreaded operation of a computer including a clock and a central processing unit having an interrupt operation so as to provide for the execution of a program having a task comprising a plurality of subtasks each performed concurrently by a respective one of a plurality of instruction threads of said program, said method comprising
  • periodically actuating said interrupt operation in response to said clock at predetermined time intervals to provide a plurality of series of spaced timeslices with a respective series of said plurality of series allocated for the execution of each thread and with the timeslices of each series of timeslices of said plurality of series interleaved with the timeslices of at least one other series of said plurality of series,
  • preempting an executing thread of said program in response to each actuation of said interrupt operation so as to terminate the timeslice of execution of said executing thread and to take control of the central processing unit away from said executing thread after the latter has executed only a portion of its respective subtask,
  • passing said control of the central processing unit to another thread of said same program and thereby invoking said another thread to perform a next successive portion of the respective subtask of said another thread during the next successive timeslice of the respective series of timeslices of said another thread,
  • thereafter returning control of the central processing unit to a previously preempted thread of said same program to enable said previously preempted thread to perform the next successive portion of its respective subtask during the next timeslice of its respective series of spaced timeslices, and
  • repeating the above-recited cycle of said clock responsive actuation of the interrupt operation, said thread preemption and said thread invocation, until the respective subtasks of the threads of said program are completed,
  • whereby each subtask portion is executed during a respective timeslice with the subtask portions of one thread interleaved with the subtask portions of at least one other thread to provide concurrent and effectively simultaneous execution of the threads.
    •


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Forward References: Show 55 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (55)   |   Backward references (0)   |   Citation Link

       
Foreign References: None

Other Abstract Info: DERABS G84-109561

Other References:
  • Cheriton, David Ross, "Multi-Process Structuring and the Thoth Operating System," Doctorial Thesis, University of Waterloo, 1978.
  • Lorin, Harold, "Parallelism in Hardware and Software, Real and Apparent Concurrency," Prentice-Hall Inc., 1972, p. 43.
  • Cheriton et al., "Thoth, a Portable Real-Time Operating System," Department of Computer Science, University of Waterloo, Mar. 1978.
  • Hiromoto, Robert, Parallel-processing a large scientific problem, AFIPS Press. 1982, pp. 235-237.
  • Ousterhout, John K., Scheduling techniques for Concurrent Systems, IEEE, 1982, pp. 22-30.
  • Andrews, Gregory R., Synchronizing Resources, ACM Transactions on Programming Languages and Systems, vol. 3, No. 4, Oct. 1981, pp. 405-430. (26 pages) Cited by 2 patents
  • Colin, A.J.T., The Implementation of STAB-1, Software -Practice and Experience, vol. 2, 1972, pp. 137-142.
  • Artym, Richard, The STAB Multiprocessing Environment for CYBA-M, Software -Practice and Experience, vol. 12, 1982, pp. 323-329. (7 pages) Cited by 2 patents
  • Treleaven et al., Combining Data Flow and Control Flow Computing, The Computer Journal, vol. 25, No. 2, 1982, pp. 207-217. (11 pages) Cited by 4 patents
  • Duffie, C. A. III, Task Scheduling Algorithm for a Teleprocessing Communications Controller, , IBM Technical Disclosure Bulletin, vol. 16, No. 10, Marcy 1974, pp. 3349-3352.
  • Hoare, C. A. R., Towards a Theory of Parallel Programming, Operating Systems Techniques, Proceedings of a Seminar held at Queen's University, Belfast, 1972, Aademic Press, 1972, pp. 61-71.


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