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 Title: |
US5719427:
Avalanche-enhanced CMOS transistor for EPROM/EEPROM and ESD-protection structures
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Tong, Paul C. F.; San Jose, CA
Hui, Chi-Hung; Cupertino, CA
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| Assignee: |
Pericom Semiconductor Corp., San Jose, CA
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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| Published / Filed: |
1998-02-17
/ 1997-01-14
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| Application Number: |
US1997000783626
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| IPC Code: |
Advanced:
H01L 27/02;
H01L 27/115;
Core:
more...
IPC-7:
H01L 23/62;
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| ECLA Code: |
H01L27/02B4F2; H01L27/115;
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| U.S. Class: |
Current:
257/355;
257/316;
257/E27.103;
Original:
257/355;
257/316;
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| Field of Search: |
257/314,315,316,927,355-363
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| Priority Number: |
| 1997-01-14 |
US1997000783626 |
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| Abstract: |
A non-volatile memory cell uses a p+ diffusion region spaced a lateral distance from the n+ drain of the n-channel programmable transistor. A diode between this p+ diffusion and the n+ drain has a low breakdown voltage because of the close spacing of the high-doping n+ and p+ diffusions. This diode generates electrons when avalanche breakdown occurs. The avalanche electrons are swept up into the programmable gate during programming. Since the avalanche electrons are generated by the diode rather than by the programmable transistor itself, programming efficiency no longer depends on the channel length and other parameters of the programmable transistor. The breakdown voltage of the diode is adjusted by varying the lateral spacing between the n+ drain and the p+ diffusion. Smaller lateral spacing enter avalanche breakdown at lower voltages and thus program the programmable transistor at a lower drain voltage. A drain voltage less than the power supply is possible with the diode, eliminating the need for a charge pump for the drain. A deep p-type implant under the n+ drain can also form the diode. The diode can be used for input-protection (ESD) devices.
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| Attorney, Agent or Firm: |
Auvinen, Stuart T. ;
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| Primary / Asst. Examiners: |
Thomas, Tom; Hardy, David B.
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| INPADOC Legal Status: |
Show legal status actions
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| Family: |
None
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First Claim:
Show all 18 claims |
We claim:
1. An avalanche-enhanced transistor comprising:
- a source diffusion of a first conductivity type in a substrate of an opposite conductivity type;
- a drain diffusion of the first conductivity type in the substrate;
- a channel region in the substrate between the source diffusion and the drain diffusion for selectively conducting current between the source diffusion and the drain diffusion;
- a control gate for controlling the current between the source diffusion and the drain diffusion; and
- an avalanche-generating diffusion of the opposite conductive type, the avalanche-generating diffusion in close proximity to the drain diffusion, wherein most of the avalanche-generating diffusion is not located directly between the source diffusion and the drain diffusion;
- wherein the avalanche-generating diffusion and the drain diffusion form an avalanche-breakdown diode;
- wherein when a critical reverse voltage bias is applied to the avalanche-breakdown diode between the drain diffusion and the avalanche-generating diffusion, an electric field between the drain diffusion and the avalanche-generating diffusion is sufficiently intense to initiate avalanche breakdown, the avalanche-breakdown diode becoming conducting in a reverse direction when the critical reverse voltage bias is applied;
- wherein the critical reverse voltage bias is less than a transistor channel-avalanche voltage when a channel bias is applied between the source diffusion and the drain diffusion, the channel bias sufficient to generate avalanche breakdown in the channel between the source diffusion and the drain diffusion,
- whereby the avalanche-generating diffusion in close proximity to the drain diffusion initiates avalanche breakdown when the critical reverse voltage bias is applied, and whereby avalanche breakdown occurs at a lower voltage in the avalanche-breakdown diode than in the channel of the avalanche-enhanced transistor.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 27 U.S. patent(s) that reference this one
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| Foreign References: |
None
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| Other References: |
"A Planar Type EEPROM Cell Structure by Standard CMOS Process for Integration With Gate Array", Ohsaki et al. 1993 IEEE CICC 23.6.1-4.
"A Flash EEPROM Cell with an Asymmetric Source and Drain Structure", Kume et al., 1987 IEDM, 25.8.
"Process and Design Optimization for Advanced CMOS I/O ESD Protection Devices" Daniel & Krieger, 1990 EOS/EDS Sympos. Proceedings, pp. 206-213.
"A Novel Programming Method for High Speed, Low Voltage Flash E2PROM Cells", Ranaweera et al., Solid-State Electronics, pp. 981-989, 1996.
(9 pages)
Cited by 2 patents
[ISI abstract]
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