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 Title: |
US5757857:
High speed self-adjusting clock recovery circuit with frequency detection
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Buchwald, Aaron W.; Marshalltown, IA
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| Assignee: |
The Regents of the University of California, Oakland, CA
other patents from UNIVERSITY OF CALIFORNIA, THE REGENTS OF (599425) (approx. 4,840)
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| Published / Filed: |
1998-05-26
/ 1996-03-13
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| Application Number: |
US1996000392958
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| IPC Code: |
Advanced:
H04L 7/027;
Core:
more...
IPC-7:
H03K 7/06;
H03K 9/06;
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| ECLA Code: |
H04L7/027C;
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| U.S. Class: |
Current:
375/271;
329/306;
329/346;
375/322;
375/326;
375/327;
375/371;
Original:
375/271;
375/322;
375/326;
375/327;
375/371;
329/346;
329/306;
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| Field of Search: |
375/261,271,279,322,324,326,327,329,344,343,354,371
329/304,306,307,345,346
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| Priority Number: |
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| Abstract: |
PCT No. PCT/US94/08223 Sec. 371 Date Mar. 13, 1996 Sec. 102(e) Date Mar. 13, 1996 PCT Filed Jul. 21, 1994 PCT Pub. No. WO96/03800 PCT Pub. Date Feb. 8, 1996A clock recovery circuit based upon an early-late gate approach is applied to high speed serial communication links using NRZ data. The circuit has no systematic phase offset and therefore requires no external phase adjustment circuits or mechanisms. The circuit is used in high speed integrated receivers for applications including fiber optics, disk-drive read/write electronics, mobile communications and high rate- twisted pair data transmission in multimedia systems. Quadrature samples are obtained and held which follow the shape of the NRZ data transition as a function of phase offset. The data signal is passed through the limiter giving rise to a sawtooth shaped phase error signal. A derivative of the error function is taken to provide a frequency error signal to provide for frequency detection and assistance in frequency acquisition of the phase lock loop circuit generating the recovered clock signal from a variably controlled oscillator.
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| Attorney, Agent or Firm: |
Dawes, Daniel L. ;
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| Primary / Asst. Examiners: |
Vo, Don N.;
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| INPADOC Legal Status: |
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Family Legal Status Report
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| Designated Country: |
CA US
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| Family: |
Show 3 known family members
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First Claim:
Show all 20 claims |
I claim:
1. A clock recovery circuit for establishing bit synchronization with an NRZ data formatted bit stream comprising:
- a matched filter for receiving said NRZ data formatted bit stream for producing a filtered output signal indicative of edge transitions in said NRZ data formatted bit stream;
- first and second sample and hold circuits having inputs coupled to said matched filter, said sample and hold circuits being complementarily clocked by a VCO signal to hold quadrature samples, said first sample and hold circuit for generating an in-phase data output signal;
- a third sample and hold circuit having an input coupled to said second sample and hold circuit, said third sample and hold circuit being clocked on positive and negative transitions of said in-phase data output signal and generating a data crossover sample;
- a multiplier for multiplying said in-phase data output signal with output from said third sample and hold circuit;
- a lowpass filter coupled to said multiplier for filtering output of said multiplier to generate a DC value of a phase error signal proportional to any phase error between said in-phase data output signal and said data crossover sample; and
- a variable controlled oscillator (VCO) having its control input coupled to said low ass filter, said variable controlled oscillator generating said VCO signal with a controllable phase according to said DC value provided by said lowpass filter, said VCO being coupled to said first and second sample and hold circuits to complementarily clock said first and second sample and hold circuits,
- whereby a data transition tracking loop is provided which is high speed, inherently self-adjusting: is independent of data transition density with significantly reduced ripple in said phase error signal generated by said multiplier.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| PCT Number: |
PCT/US94/08223
WO9603800
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| PCT Pub./Filed Dates: |
1996-02-08 / 1994-07-21
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| § 371 / 102(e) Dates: |
1996-03-13 / 1996-03-13
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| Forward References: |
Show 49 U.S. patent(s) that reference this one
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