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 Title: |
US5781750:
Dual-instruction-set architecture CPU with hidden software emulation mode
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Blomgren, James S.; San Jose, CA
Richter, David E.; San Jose, CA
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| Assignee: |
Exponential Technology, Inc., San Jose, CA
other patents from EXPONENTIAL TECHNOLOGY, INC. (713599) (approx. 34)
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| Published / Filed: |
1998-07-14
/ 1994-01-11
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| Application Number: |
US1994000179926
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| IPC Code: |
Advanced:
G06F 9/30;
G06F 9/318;
G06F 9/38;
G06F 9/455;
G06F 12/02;
Core:
more...
IPC-7:
G06F 9/455;
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| ECLA Code: |
G06F9/38T2; G06F9/30T; G06F9/318; G06F9/318T; G06F9/455H;
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| U.S. Class: |
Current:
712/209;
703/026;
712/229;
712/E09.028;
712/E09.035;
712/E09.037;
712/E09.072;
Original:
395/385;
395/500;
395/570;
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| Field of Search: |
395/385,500,800.43,570,800.23,800.41
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| Priority Number: |
| 1994-01-11 |
US1994000179926 |
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| Abstract: |
A dual-instruction-set CPU is able to execute x86 CISC (complex instruction set computer) code or PowerPC RISC (reduced instruction set computer) code. Three modes of operation are provided: CISC mode, RISC mode, both called user modes, and emulation mode. Emulation mode is entered upon reset, and performs various system checks and memory allocation. A special emulation driver is loaded into a portion of main memory set aside at reset. Software routines to emulate the more complex instructions of the CISC architecture using RISC instructions are also loaded into the emulation memory. A TLB is enabled, and translation tables and drivers are set up in the emulation memory. All TLB misses, even in the user modes, will cause entry to a translator driver in emulation mode. Since the TLB is always enabled for the user modes, and all misses are handled by the emulation code, the emulation code can set aside a portion of memory for itself and insure that the user programs never have access to the emulation memory. Thus the programs, including operating systems, in CISC or RISC mode are unaware of emulation memory or even the existence of emulation mode.
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| Attorney, Agent or Firm: |
Auvinen, Stuart T. ;
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| Primary / Asst. Examiners: |
Lall, Parshotam S.; Vu, Viet
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| INPADOC Legal Status: |
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| Family: |
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First Claim:
Show all 20 claims |
We claim:
1. A central processing unit (CPU) for processing instructions from two separate instruction sets, said CPU comprising:
- first instruction decode means for decoding instructions from a first instruction set, said first instruction set having a first encoding of instructions;
- second instruction decode means for decoding only a subset of instructions from a second instruction set, said second instruction set having a second encoding of instructions, said first encoding of instructions independent from said second encoding of instructions;
- select means, coupled to said first instruction decode means and said second instruction decode means, for selecting said decoded instruction from either said first instruction decode means or from said second instruction decode means; and
- execute means for executing decoded instructions selected by said select means,
- whereby instructions from both said first instruction set and said second instruction set are executed by said CPU.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 65 U.S. patent(s) that reference this one
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