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 Title: |
US5787465:
Destination indexed miss status holding registers
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Jouppi, Norman P.; Palo Alto, CA
Haddad, Ramsey W.; Cupertino, CA
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| Assignee: |
Digital Equipment Corporation, Maynard, MA
other patents from DIGITAL EQUIPMENT CORPORATION (147695) (approx. 2,345)
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| Published / Filed: |
1998-07-28
/ 1996-08-21
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| Application Number: |
US1996000701036
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| IPC Code: |
Advanced:
G06F 9/312;
G06F 9/38;
G06F 12/08;
Core:
more...
IPC-7:
G06F 12/00;
G06F 12/08;
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| ECLA Code: |
G06F9/312; G06F9/38D; G06F12/08B6P4;
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| U.S. Class: |
Current:
711/117;
711/003;
711/118;
711/146;
711/E12.051;
712/E09.033;
712/E09.046;
Original:
711/117;
364/DIG.1;
364/DIG.2;
364/243.4;
711/003;
711/118;
711/146;
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| Field of Search: |
395/444,445,446,451,473,458
364/DIG. 1,DIG. 2,243.4,243.41
711/117,118,131,146,3
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| Priority Number: |
| 1996-08-21 |
US1996000701036 |
| 1994-07-01 |
US1994000270080 |
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| Abstract: |
A hierarchical memory arrangement for use with a processor includes a cache, addressable by source addresses, and a set of processor registers, addressable by destination addresses. For each processor register there is a miss status holding registers. If the cache does not store data requested for one of the processor registers, a miss condition is generated. In response to the miss condition, the address of a cache block to contain the missing data is stored in the miss status holding register corresponding to the processor register for which the data are requested. While the requested data are transferred from a main memory to the cache, the cache is not locked up and additional data accesses are allowed.
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| Attorney, Agent or Firm: |
Brinkman, Dirk ;
Johnston, A. Sidney ;
Stadnicki, Alfred A. ;
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| Primary / Asst. Examiners: |
Swann, Tod R.; Thai, Tuan V.
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| INPADOC Legal Status: |
Show legal status actions
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| Parent Case: |
This application is a continuation of application Ser. No. 08/270,080, filed Jul. 1, 1994, now abandoned.
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| Family: |
None
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First Claim:
Show all 12 claims |
We claim:
1. A hierarchical memory arrangement for use with a computer system including a main memory, a cache memory, and a processor having a set of processor registers, comprising:
- a set of status registers, there being one status register corresponding to each processor register;
- means, responsive to the processor requesting the transfer of data stored in the cache memory at a source address to one of the processor registers having a destination address, for determining a miss condition of the data-stored at the source address;
- means, responsive to detecting the miss condition, for selecting a particular status register corresponding to the one processor register having the destination address wherein the source address is stored in said particular status register which corresponds to the destination address; and
- means for storing the source address in the particular status register corresponding to the one processor register having the destination address, and for initiating the transfer of the data from the main memory to the cache memory at the source address while allowing the processor to request the transfer of additional data from the cache memory at different source addresses to the set of processor registers.
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| Background / Summary: |
Show background / summary
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| Drawing Descriptions: |
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| Description: |
Show description
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| Forward References: |
Show 4 U.S. patent(s) that reference this one
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| Foreign References: |
None
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| Other Abstract Info: |
DERABS G98-436971
DERG98-436971
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| Other References: |
Kroft, D., "Lockup-Free Instruction Fetch/Prefetch Cache Organization", 1981 IEEE, pp. 81-87.
"Memory Access Dependencies in Shared Memory Multiprocessors", M. Dubois and C. Scheurich, IEEE Trans. Software Eng., Jun. 1990.
"The Design of a Lookup-Free Cache", M. Dubois and c. Scheurich, IEEE, 1990, pp. 352-389.
"Lockup-Free Caches in High Performance Multiprocessors", C. Scheurich and M. Dubois, J. of Parallel and Distributed Computing, vol. 11, 1991, pp. 25-36.
(12 pages)
[ISI abstract]
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