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 Title: |
US5796715:
Non-blocking dynamic fast packet switch for satellite communication system
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Patterson, David Palmer; Los Altos, CA
Liron, Moshe L.; Palo Alto, CA
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| Assignee: |
Teledesic Corporation, Kirkland, WA
other patents from TELEDESIC CORPORATION (710519) (approx. 10)
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| Published / Filed: |
1998-08-18
/ 1994-05-12
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| Application Number: |
US1994000241984
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| IPC Code: |
Advanced:
H04B 7/185;
H04L 12/56;
H04Q 11/04;
Core:
more...
IPC-7:
H04L 12/56;
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| ECLA Code: |
H04L12/56A; H04B7/185S10; H04B7/185S12; H04L12/56C; H04Q11/04S2; T04L12/56S5; T04L12/56W6; T04L12/56A2C6; T04L12/56A2G2; T04L12/56A4B4; T04L12/56A18D4; T04L12/56A18D5; T04L12/56A22D; T04W40/20;
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| U.S. Class: |
Current:
370/349;
370/323;
370/389;
455/012.1;
Original:
370/060;
370/094.1;
455/012.1;
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| Field of Search: |
370/060,94.1,60.1,95.1,95.3,54,58.2
455/33.1-33.4,56.1,12.1,13.1,13.2,13.3,13.4,17,38.3
379/059,60,61,58
364/449,450
342/354,357
244/158.12
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| Priority Number: |
| 1994-05-12 |
US1994000241984 |
| 1991-11-08 |
US1991000790805 |
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| Abstract: |
The present invention overcomes the limitations encountered by conventional packet switching using virtual circuits. The present invention utilizes a "datagram" approach that routes every packet (22) conveyed by the system independently at every node in the network. The packets (22) are directed along an optimized pathway through the network by a fast packet switch (38) that directs traffic based on instructions from an adaptive routing processor (12A) that continuously runs an adaptive routing software (12B). This adaptive routing processor (14) supplies an output (12C) to a routing cache memory (20) which stores fast packet switch routing port output tags (30). An input packet processor (28) extracts a supercell address from the header (24) of each packet (22) and uses the supercell address (21A) as an index to retrieve a fast packet switch output port tag (30) stored in the routing cache memory (20). This tag (30) is prepended to the packet (22), and sent to an input port (36) of the fast packet switch (38), which includes a number of multi-stage self-routing switch modules (132) and a number of asynchronous packet multiplexors (134). The modules (132) and multiplexors (134) route the tagged packet (34) to an output port (40) which is connected either to a scanning beam antenna (SBA) or an intersatellite link antenna (ISA).
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| Attorney, Agent or Firm: |
Anglin & Giaccherini ;
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| Primary / Asst. Examiners: |
Ton, Dang;
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| INPADOC Legal Status: |
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Family Legal Status Report
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| Parent Case: |
This application is a continuation in part of Ser. No. 07/790,805 filed Nov. 8, 1991, now abandoned.
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| Designated Country: |
BB BG BR CA CS FI HU JP KP KR LK LU MG MN MW NO OA PL RO RU SD UA BE CH DK ES FR GB GR IE IT LI NL SE
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| Family: |
Show 10 known family members
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| Claim |
What is claimed is:
1. Apparatus for directing a packet (22) having a header (24) and a payload (26) onboard a satellite (S) in earth orbit comprising:
- an autonomous orbit determination microprocessor (11A);
- said autonomous orbit determination microprocessor (11A) having a stored and continuously running autonomous orbit determination software (11B);
- said autonomous orbit determination microprocessor (11A) further having an output containing orbital position information (11C);
- an adaptive routing microprocessor (12A);
- said adaptive routing microprocessor (12A) being coupled to said autonomous orbit determination microprocessor (11A);
- said adaptive routing microprocessor (12A) having a stored and continuously running adaptive routing software (12B);
- said adaptive routing microprocessor (12A) having an output containing a next-node-in-path-to-destination output (12C) derived from said output containing orbital position information (11C);
- a routing cache memory (20);
- said routing cache memory (20) being coupled to said output of said adaptive routing microprocessor (12A), containing a next-node-in-path-to-destination output (12C);
- said routing cache memory (20) having a plurality of fast packet switch output port tags (30) stored in memory, each of said fast packet switch output port tags (30) being indexed by a supercell address (21A) which is part of said header (24);
- an input packet processor (28);
- said input packet processor (28) being coupled to said routing cache memory (20);
- said input packet processor (28) having an input (27) through which said packet (22) is received;
- said input packet processor (28) having a software program which extracts said supercell address (21A) from said header (24) of said packet (22);
- said input packet processor (28) further having a software program which uses said supercell address (21A) as an index to read one of said plurality of fast packet switch output port tags (30) from said routing cache memory (20);
- said input packet processor (28) also having a packet tagger (31); said packet tagger having an output in which one of said fast packet switch output port tags (30) is prepended to said packet (22) to create a tagged packet (34); and
- a fast packet switch (38);
- said fast packet switch (38) including
- a plurality of input ports (36), through one of which said plurality of input ports (36), said tagged packet (34) is received;
- a plurality of output ports (40);
- a plurality of multi-stage self-routing switch modules (132);
- a plurality of asynchronous packet multiplexors (134); said plurality of asynchronous packet multiplexors (134) being coupled to said plurality of multi-stage self-routing switch modules (132); and
- said plurality of multi-stage self-routing switch modules (132) and said plurality of asynchronous packet multiplexors (134) cooperating together to uniquely route said tagged packet (34) to one of said plurality of output ports (40) without contention with any other tagged packet (34).
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 26 U.S. patent(s) that reference this one
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