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 Title: |
US5930254:
Non-blocking dynamic fast packet switch for satellite communication system
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Liron, Moshe L.; Palo Alto, CA
Patterson, David Palmer; Bellevue, WA
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| Assignee: |
Teledesic LLC, Kirkland, WA
other patents from TELEDESIC LLC (746777) (approx. 21)
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| Published / Filed: |
1999-07-27
/ 1997-10-15
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| Application Number: |
US1997000950971
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| IPC Code: |
Advanced:
H04B 7/185;
H04L 12/56;
Core:
more...
IPC-7:
H04L 12/56;
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| ECLA Code: |
H04B7/185S12; H04L12/56S4; T04L12/56S1A; T04L12/56S2B; T04L12/56S3B; T04L12/56S5A;
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| U.S. Class: |
Current:
370/238.1;
370/389;
Original:
370/395;
370/389;
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| Field of Search: |
370/389,395,397,412,428,310,349,350,323,351,352,353,465,474,471,376,372,370,369,360,361,367,388,387
342/354,357
244/158.12
455/3.2,456,12.1,13.2
379/219
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| Priority Number: |
| 1997-10-15 |
US1997000950971 |
| 1994-05-12 |
US1994000241984 |
| 1991-11-08 |
US1991000790805 |
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| Abstract: |
The present invention overcomes the limitations encountered by conventional packet switching using virtual circuits. The present invention utilizes a "datagram" approach that routes every packet (22) conveyed by the system independently at every node in the network. The packets (22) are directed along an optimized pathway through the network by a fast packet switch (38) that directs traffic based on instructions from an adaptive routing processor (12A) that continuously runs an adaptive routing software (12B). This adaptive routing processor (14) supplies an output (12C) to a routing cache memory (20) which stores fast packet switch routing port output tags (30). An input packet processor (28) extracts a supercell address from the header (24) of each packet (22) and uses the supercell address (21A) as an index to retrieve a fast packet switch output port tag (30) stored in the routing cache memory (20). This tag (30) is prepended to the packet (22), and sent to an input port (36) of the fast packet switch (38), which includes a number of multi-stage self-routing switch modules (132) and a number of asynchronous packet multiplexors (134). The modules (132) and multiplexors (134) route the tagged packet (34) to an output port (40) which is connected either to a scanning beam antenna (SBA) or an intersatellite link antenna (ISA).
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| Attorney, Agent or Firm: |
Christensen O'Connor Johnson & Kindness PLLC ;
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| Primary / Asst. Examiners: |
Ton, Dang;
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| Maintenance Status: |
E1 Expired Check current status
CC Certificate of Correction issued
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| INPADOC Legal Status: |
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Family Legal Status Report
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| Parent Case: |
This application is a continuation of U.S. application Ser. No. 08/241,984, filed on May 12, 1994, now U.S. Pat. No. 5,796,715, which was a continuation-in-part of U.S. application Ser. No. 07/790,805, filed on Nov. 8, 1991, now abandoned. Priority of the filing dates of such earlier applications is claimed under 35 U.S.C. §120.
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| Designated Country: |
BB BG BR CA CS FI HU JP KP KR LK LU MG MN MW NO OA PL RO RU SD UA BE CH DK ES FR GB GR IE IT LI NL SE
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| Family: |
Show 10 known family members
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First Claim:
Show all 7 claims |
What is claimed is:
1. A apparatus for directing a packet (22) having a header (24) and a payload (26) onboard a satellite (S) in earth orbit comprising:
- an autonomous orbit determination microprocessor (11A);
- said autonomous orbit determination microprocessor (11A) being capable of storing and continuously running an autonomous orbit determination software (11B);
- said autonomous orbit determination microprocessor (11A) further being capable of producing an output containing orbital position information (11C);
- an adaptive routing microprocessor (12A);
- said adaptive routing microprocessor (12A) being coupled to said autonomous orbit determination microprocessor (11A);
- said adaptive routing microprocessor (12A) being capable of storing and continuously running an adaptive routing software (12B);
- said adaptive routing microprocessor (12A) further being capable of using said orbital position information output (11C) from said autonomous orbit determination microprocessor (11A) to produce an output containing a next-node-in-path-to-destination output (12C);
- a routing cache memory (20);
- said routing cache memory (20) being coupled to said adaptive routing microprocessor (12A);
- said routing cache memory (20) being capable of receiving said next-node-in-path-to-destination output (12C) from said adaptive routing microprocessor (12A);
- said routing cache memory (20) also being capable of storing a plurality of fast packet switch output port tags (30) which are each indexed by a supercell address (21A);
- an input packet processor (28);
- said input packet processor (28) being coupled to said routing cache memory (20);
- said input packet processor (28) being capable of receiving said packet (22);
- said input packet processor (28) also being capable of extracting said supercell address (21A) from said header (24) of said packet (22);
- said input packet processor (28) further being capable of using said supercell address (21A) as an index to read one of said plurality of fast packet switch output tags (30) from said routing cache memory (20);
- said input packet processor (28) also having a packet tagger (30); said packet tagger (30) being capable of prepending one of said fast packet switch output port tags (30) to said packet (22) to create a tagged packet (34); and
- a fast packet switch (38);
- said fast packet switch (38) being capable of receiving said tagged packet (34) and including
- a plurality of input ports (36);
- a plurality of output ports (40);
- a plurality of multi-stage self-routing switch modules (132);
- a plurality of asynchronous packet multiplexors (134); said plurality of asynchronous packet multiplexors (134) being coupled to said plurality of multi-stage self-routing switch modules (132); and
- said plurality of multi-stage self-routing switch modules (132) and said plurality of asynchronous packet multiplexors (134) being capable of routing said tagged packet (34) one of said plurality of output ports (40).
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 22 U.S. patent(s) that reference this one
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| Foreign References: |
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PDF |
Publication |
Date |
IPC Code |
Assignee |
Title |
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EP0385885A3
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1990-02 |
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| Other Abstract Info: |
DERABS G1999-443179
DERABS G1999-443179
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| Other References: |
Delli Priscoll et al., "Access and Switching Techniques in an ATM User-Oriented Satellite System," IEEE Infocom '89 Proceedings, vol. 2, CH2702-9/89/0000/0632, Apr. 1989, pp. 0632-0640.
Enrico Del Re et al., "A Fast Packet Swithcing Satellite Communication Network," IEEE Inforcom '91 Proceedings, vol. 2, CH2979-3/91/0000-1445, Apr. 1991, pp. 0445-0453.
Koji Suzuki et al.,"An ATM Switching System-Development and Evaluation," NEC Research and Development, vol. 32, No. 2, Apr. 1991, pp. 242-251.
(10 pages)
Cited by 2 patents
[ISI abstract]
Nachum Shacham, "Protocols for Multi-Satellite Networks," IEEE Milcom '88 Proceedings, vol. 2, CH2557-9/88/0-0001, Oct. 1988, pp. 0501-0505.
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