 |
|
|
|
|
|
 Title: |
US5943382:
Dual-loop spread-spectrum clock generator with master PLL and slave voltage-modulation-locked loop
[ Derwent Title ]
|
| Country: |
US United States of America
|
| |
| Inventor: |
Li, Hung-Sung; Santa Clara, CA
Pimpalkhare, Mangesh S.; Santa Clara, CA
|
| Assignee: |
NeoMagic Corp., Santa Clara, CA
other patents from NEOMAGIC CORP. (719584) (approx. 58)
News, Profiles, Stocks and More about this company
|
| Published / Filed: |
1999-08-24
/ 1997-12-15
|
| Application Number: |
US1997000990899
|
| IPC Code: |
Advanced:
G09G 3/20;
G09G 5/00;
G09G 5/18;
G09G 5/36;
H03L 7/07;
H05K 9/00;
G06F 3/14;
G09G 3/36;
Core:
more...
IPC-7:
H03D 3/24;
|
| ECLA Code: |
G09G3/20; G09G5/18; H03L7/07; H05K9/00G; S09G5/00T4C; S09G217/00;
|
| U.S. Class: |
Current:
375/376;
375/375;
Original:
375/376;
375/200;
375/375;
|
| Field of Search: |
375/200,204,375,376
331/7.8
332/144
|
| Priority Number: |
|
| Abstract: |
A clock generator produces a frequency-modulated clock. A master phase-locked loop (PLL) includes a voltage summer that outputs a voltage to a voltage-controlled oscillator (VCO). The voltage to the VCO determines the frequency of the clock generated. A modulated voltage is subtracted by the voltage summer to produce voltage and thus frequency modulations. This modulated voltage is produced by a second loop that operates as a slave to the master PLL. The slave loop is a voltage-locked loop. The peak amplitude of the modulated voltage is locked to a control voltage of the master PLL. The control voltage is a stable voltage input to the voltage summer that is generated by phase comparisons of the output clock to a reference clock. To overcome the problem of locking to the modulating output clock, phase comparison is performed only at the same point in the modulation cycle, at the beginning of each modulation cycle. Thus modulations do not affect phase comparisons. The modulated voltage is generated by a waveform generator in the slave loop. The waveform generator is controlled by a feedback divider that also controls when phase comparison is performed. The amplitude of the waveform is adjusted to track the control voltage of the master PLL by comparing the control voltage to the modulated voltage, but only at the beginning of the modulation cycle. The modulation amplitude is kept constant over different supply voltages, ambient temperatures, and process corners.
|
| Attorney, Agent or Firm: |
Auvinen, Stuart T. ;
|
| Primary / Asst. Examiners: |
Chin, Stephan; Fan, Chieh M.
|
| INPADOC Legal Status: |
Show legal status actions
Family Legal Status Report
|
|
|
|
|
|
|
| Parent Case: |
RELATED APPLICATION
This is a Continuation-in-Part (CIP) of "EMI Reduction for a Flat-Panel Display Controller Using Horizontal-Line-Based Spread Spectrum", U.S. Ser. No. 08/701,814, filed Aug. 21, 1996, now U.S. Patent No. 5,757,338.
|
| Family: |
Show 4 known family members
|
First Claim:
Show all 20 claims |
We claim:
1. A modulated clock generator comprising:
- a master phase-locked loop (PLL), receiving a reference clock and outputting a modulated clock, the master PLL comprising:
- a feedback divider, receiving the modulated clock, for generating a pulse after every M cycles of the modulated clock;
- a phase comparator, receiving the reference clock and the pulse from the feedback divider, for comparing a phase of the reference clock to a phase of the pulse when the pulse is received, the phase comparator outputting a phase-difference signal;
- a summer, receiving the phase-difference signal from the phase comparator, for combining a modulated signal with the phase-difference signal to generate a frequency-determining signal;
- a frequency generator for generating the modulated clock having a frequency determined by the frequency-determining signal from the summer, the frequency varying over time when the modulated signal varies over time; and
- a slave voltage-locked loop (VLL) comprising:
- a waveform generator, coupled to the feedback divider, for generating the modulated signal to the summer in the master PLL, the modulated signal being synchronized to the pulse from the feedback divider;
- a slave comparator, receiving the phase-difference signal from the phase comparator and receiving the modulated signal from the waveform generator, for outputting a difference signal when the phase-difference signal has a same voltage as the modulated signal;
- a second phase comparator, coupled to supply a level signal to the waveform generator, for comparing the difference signal from the slave comparator to the pulse from the feedback divider when the pulse is received,
- whereby the slave VLL generates the modulated signal for the master PLL.
|
| Background / Summary: |
Show background / summary
|
| Drawing Descriptions: |
Show drawing descriptions
|
| Description: |
Show description
|
| Forward References: |
Show 37 U.S. patent(s) that reference this one
|
|
|
|
|
|
|
| U.S. References: |
Go to Result Set:
All U.S. references
| Forward references (37)
|
Backward references (18)
|
Citation Link
Buy
PDF |
Patent |
Pub.Date |
Inventor |
Assignee |
Title |
 |
US4574243 |
1986-03 |
Levine |
Motorola, Inc. |
Multiple frequency digital phase locked loop
|
|
|
US5072298 |
1991-12 |
Sumiyoshi |
Kabushiki Kaisha Toshiba |
Auto-tuning circuit for an active filter used in video signal processing
|
|
|
US5113152 |
1992-05 |
Norimatsu |
NEC Corporation |
PLL frequency synthesizer with circuit for changing loop filter time constant
|
|
|
US5144156 |
1992-09 |
Kawasaki |
Seiko Epson Corporation |
Phase synchronizing circuit with feedback to control charge pump
|
|
|
US5166641 |
1992-11 |
Davis et al. |
National Semiconductor Corporation |
Phase-locked loop with automatic phase offset calibration
|
|
|
US5329250 |
1994-07 |
Imaizumi et al. |
Sanyo Electric Co., Ltd. |
Double phase locked loop circuit
|
|
|
US5334953 |
1994-08 |
Mijuskovic |
Motorola, Inc. |
Charge pump bias control in a phase lock loop
|
|
|
US5446416 |
1995-08 |
Lin et al. |
Industrial Technology Research Institute |
Time acquisition system with dual-loop for independent frequency phase lock
|
|
|
US5488627 |
1996-01 |
Hardin et al. |
Lexmark International, Inc. |
Spread spectrum clock generator and associated method
|
|
|
US5491458 |
1996-02 |
McCune, Jr. et al. |
|
Apparatus for spreading the spectrum of a signal and method therefor
|
|
|
US5506545 |
1996-04 |
Andrea |
GTE Government Systems Corporation |
Electronic apparatus having low radio frequency interference from controlled excursion noise-modulated system clock signal
|
|
|
US5521947 |
1996-05 |
Madsen |
National Semiconductor Corporation |
Phase detection reset in phase locked loops used for direct VCO modulation
|
|
|
US5610558 |
1997-03 |
Mittel et al. |
Motorola, Inc. |
Controlled tracking of oscillators in a circuit with multiple frequency sensitive elements
|
|
|
US5610955 |
1997-03 |
Bland |
Microclock, Inc. |
Circuit for generating a spread spectrum clock
|
|
|
US5614855 |
1997-03 |
Lee et al. |
Rambus, Inc. |
Delay-locked loop
|
|
|
US5631920 |
1997-05 |
Hardin |
Lexmark International, Inc. |
Spread spectrum clock generator
|
|
|
US5659587 |
1997-08 |
Knierim |
Tektronix, Inc. |
Spread spectrum phase-locked loop clock generator with VCO driven by a symmetrical voltage ramp signal
|
|
|
US5675291 |
1997-10 |
Sudjian |
National Semiconductor Corporation |
Phase-lock loop with reduced acquistion time
|
|
|
|
|
|
|
|
| Foreign References: |
None
|
| Other Abstract Info: |
DERABS G1999-493661
DERABS G1999-493661
DERABS G2000-327916
DERABS G2000-375003
|
| Other References: |
Hardin et al., "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions," Proceedings of IEEE International Symposium on Electromagnetic Compatibility, pp. 227-231, Apr. 4, 1994.
Clark et al., "Application of a PLL and All Noise Reduction Process in Optical Sensing Systems," IEEE Transactions on Industrial Electronics, pp. 136-138, Feb. 1994.
Dussarrat et al., "A New Demodulation Process to Reduce Cochannel Interference for a laser Vibrometer Sensing System," Proceedings of the SPIE, vol. 3411, pp. 2-13, Jun. 1998.
|
|
 Nominate this for the Gallery...
|
|
