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 Title: |
US5958040:
Adaptive stream buffers
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Jouppi, Norman P.; Palo Alto, CA
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| Assignee: |
Digital Equipment Corporation, Maynard, MA
other patents from DIGITAL EQUIPMENT CORPORATION (147695) (approx. 2,345)
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| Published / Filed: |
1999-09-28
/ 1997-05-28
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| Application Number: |
US1997000864125
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| IPC Code: |
Advanced:
G06F 9/38;
G06F 12/08;
Core:
more...
IPC-7:
G06F 12/00;
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| ECLA Code: |
G06F9/38D2; G06F9/38F; G06F12/08B8;
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| U.S. Class: |
Current:
712/207;
711/122;
711/133;
711/137;
711/159;
711/213;
711/218;
711/E12.057;
712/E09.047;
712/E09.055;
Original:
712/207;
711/122;
711/133;
711/137;
711/159;
711/213;
711/218;
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| Field of Search: |
395/381,382,383
711/005,122,137,157,213,221,118,119,125,133,140,159,169,204,218
712/205,206,207
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| Priority Number: |
| 1997-05-28 |
US1997000864125 |
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| Abstract: |
The invention is a system providing adaptive stream buffers using instruction-specific prefetching avoidance (ISPA). According to the invention, each time the CPU executes an instruction resulting in prefetched cache lines not being used, the instruction address is stored in a table. Subsequent instruction addresses are compared to the instruction addresses in the table, and a stream buffer is not allocated when the subsequent instruction address is found within the table.
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| Attorney, Agent or Firm: |
Cesari and McKenna, LLP ;
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| Primary / Asst. Examiners: |
Treat, William M.;
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| INPADOC Legal Status: |
Show legal status actions
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| Family: |
None
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First Claim:
Show all 11 claims |
I claim:
1. A method for prefetching data to a computer readable memory for possible use by a processor, the method comprising the steps of:
- a) providing a table for storing unproductive prefetch instruction addresses;
- b) for each memory reference instruction issuino from the processor that encounters a cache miss, performing the following steps:
- i) deternining whether an instruction address of the issued instruction matches any of the unproductive prefetch instruction addresses stored in the table;
- ii) selectively allocating the computer readable memory to prefetch data only when the instruction address of the issued instruction does not match any of the unproductive prefctch instruction addresses stored in the table;
- iii) determining whether data prefetched for the issued instruction is productive; and
- iv) selectively storing the instruction address of the issued instruction in the table as an unproductive prefetch instruction address only when data prefetched for the issued instruction is not productive.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 41 U.S. patent(s) that reference this one
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