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Title: US5959871: Programmable analog array circuit
[ Derwent Title ]

Country: US United States of America

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35 pages

 
Inventor: Pierzchala, Edmund; Milwaukie, OR
Perkowski, Marek A.; Beaverton, OR

Assignee: Analogix/Portland State University, Portland, OR
other patents from ANALOGIX (758892) (approx. 1)
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Published / Filed: 1999-09-28 / 1994-12-22

Application Number: US1994000362838
IPC Code: Advanced: G06G 7/06;
Core: G06G 7/00;
IPC-7: H03K 17/693;

ECLA Code: G06G7/06;

U.S. Class: Current: 703/004; 327/565; 716/016; 716/017;
Original: 364/489; 327/565; 326/039;

Field of Search: 364/488,489,490 326/039,41 327/341,526,566,565

Priority Number:
1994-12-22  US1994000362838
1993-12-23  US1993000173414

Abstract: There is disclosed a programmable analog or mixed analog/digital circuit. More particularly, this invention provides a circuit architecture that is flexible for a programmable electronic hardware device or for an analog circuit whose input and output signals are analog or multi-valued in nature, and primarily continuous in time. There is further disclosed a design for a current-mode integrator and sample-and-hold circuit, based upon Miller effect.

Attorney, Agent or Firm: Oster, Jeffrey B. ;

Primary / Asst. Examiners: Trans, Vincent N.;

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Related Applications:
Application Number Filed Patent Pub. Date  Title
US1993000173414 1993-12-23       


       
Parent Case:

CROSS REFERENCE TO RELATED APPLICATION
    This patent application is a continuation-in-part of U.S. patent application Ser. No. 08/173,414 filed Dec. 23, 1993 now abandoned.

Designated Country: AU CA EP JP KR 

Family: Show 3 known family members
First Claim:
Show all 6 claims		 We claim:     1. A programmable analog device comprising an array of programmable analog signal processing cells, wherein each analog signal processing cell comprises an analog signal processing portion and a control circuit, wherein the control circuit controls the operation of the analog signal processing portion and may also take part in auxiliary information processing, wherein the array of programmable analog signal processing cells are locally interconnected by one or a plurality of signal interconnections to form the programmable analog device, wherein a cell is considered locally interconnected in that the number of cells connected to a given cell by programmable analog signal connections connected to the cell does not change as the number of cells in the programmable analog device varies, whereby a total length of unprogrammed signal connections has been minimized.

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Forward References: Show 42 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (42)   |   Backward references (11)   |   Citation Link

Buy
PDF		 Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 25pp US4870302  1989-09 Freeman  Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
Buy PDF- 32pp US4873459  1989-10 El Gamal  Actel Corporation Programmable interconnect architecture
Buy PDF- 32pp US4918440  1990-04 Furtek   Programmable logic cell and array
Buy PDF- 8pp US5047655  1991-09 Chambost et al.  Thomson - CSF Programmable analog neural network
Buy PDF- 13pp US5107146  1992-04 El-Ayat  Actel Corporation Mixed mode analog/digital programmable interconnect architecture
Buy PDF- 14pp US5189321  1993-02 Seevinck  U.S. Philips Corporation Companding current-mode transconductor-C integrator
Buy PDF- 31pp US5196740  1993-03 Austin  Pilkington Micro-Electronics Limited Integrated circuit for analogue system
Buy PDF- 13pp US5245565  1993-09 Petersen et al.  International Microelectronic Products Digitally programmable linear phase filter having phase equalization
Buy PDF- 13pp US5325317  1994-06 Petersen et al.  International Microelectronic Products Digitally programmable linear phase filter having phase equalization
Buy PDF- 16pp US5336937  1994-08 Sridhar et al.  State University of New York Programmable analog synapse and neural networks incorporating same
Buy PDF- 6pp US5361040  1994-11 Barrett  Motorola, Inc. Self limiting and self biasing operational transconductance amplifier
       
Foreign References: None

Other Abstract Info: DERABS G1995-240843 DERABS G1999-561169 DERABS G1999-561169

Other References:
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  • Sivilotti, Advanced Res. VLSI, Proc. Fifth MIT Conf., ed. Leighton, pp. 237-258, MIT Press, Cambridge, MA, 1988.
  • Van der Spiegel et al., J. Solid-State Circ. 27:82-92, 1992.
  • Vallancourt and Tsividis, IEEE ISSCC Dig. Tech. Papers, pp. 208-209, 1987.
  • Varrientos et al., IEEE Trans. on Cir. Sys. II 40:147-155, 1993. (9 pages) [ISI abstract]
  • Baktir and Tan, IEEE Trans. Cir. Sys. 40:200-206, 1993. (7 pages) [ISI abstract]
  • Dalla Betta et al., IEEE Trans. Cir. Sys. 40:206-215, 1993. (10 pages) [ISI abstract]
  • van den Broeke and Nieuwkerk, IEEE J. Solid-State Cir. 28:862-864, 1993. (3 pages) Cited by 8 patents [ISI abstract]
  • Chua and Roska, IEEE Trans. Cir. Sys. I 40:147-156, 1993. (10 pages) [ISI abstract]
  • Ismail et al., IEEE J. Solid-State Cir. 23:183-194, 1988. (12 pages) Cited by 4 patents
  • Krieg et al., ISCAS, pp. 958-961, IEEE, 1990.
  • Lee and Gulak, 1991 IEEE ISSCC Dig. Tech. Papers, 34:186-187, 1991. [Lee and Gulak I].
  • Lee and Gulak, IEEE J. Solid-State Circ., 26:1860-1867, 1991. [Lee and Gulak II]. (8 pages) Cited by 7 patents [ISI abstract]
  • Lee and Gulak, Electronics Lett. 28:28-29, 1992. [Lee and Gulak III]. (2 pages) [ISI abstract]
  • Lee and Gulak, Proc. EPGA '94 Workshop, ACM, Berkely, CA, 1994. [Lee and Gulak IV].
  • Loh and Geiger, ISCAS, pp. 2248-2251, Singapore, 1991.
  • Loh et al., IEEE Trans. Cir. Sys. 39:265-276, 1992. (12 pages) [ISI abstract]
  • Manetti and Piccirilli, Proc. 6th Mediterranean ELectrotechnical Conference, pp. 355-358, Ljubljana, Yugoslavia, 1991.
  • Mashiko et al., ISCAS, pp. 1279-1282, 1991.
  • Chua and Yang, IEEE Trans. Cir. Sys. pp. 1257-1272, 1988. [Chua and Yang I]. (16 pages) Cited by 5 patents
  • Chua and Yang, IEEE Trans. Cir. Sys. pp. 1273-1290, 1988. [Chua and Yang II]. (18 pages) Cited by 5 patents
  • Cimagalli et al., IEEE Trans. Cir. Sys. II, 40:174-183, 1993. (10 pages) [ISI abstract]
  • Intel Corp., 80170NX, Electrically Trainable Analog Neural Network, Santa Clara, Calif., 1991.
  • Cruz and Chua, IEEE Trans. Cir. Sys. 38:812-817, 1991. (6 pages) Cited by 3 patents [ISI abstract]
  • EL Gamal et al., IEEE J. Solid-State Circ. 24:394-398, 1989.
  • Gilbert, IEEE ISSCC Dig. Tech. Papers, pp. 286-287, 1984. (2 pages)
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  • Harrer et al., IEEE Trans. Neural Networks 3:466-476, 1992. (11 pages) [ISI abstract]
  • PMI, GAP-01, Analog Signal Processing Subsystem.


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