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 Title: |
US5963736:
Software reconfigurable target I/O in a circuit emulation system
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Sarno, Tony R.; Scotts Valley, CA
Schaefer, Ingo; Sunnyale, CA
Chilton, John E.; Soquel, CA
Papamarcos, Mark S.; San Jose, CA
Blanding, Curt; San Jose, CA
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| Assignee: |
Quickturn Design Systems, Inc., Mountainview, CA
other patents from QUICKTURN DESIGN SYSTEMS, INC. (712089) (approx. 49)
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| Published / Filed: |
1999-10-05
/ 1997-03-03
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| Application Number: |
US1997000805852
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| IPC Code: |
Advanced:
G06F 11/22;
G06F 17/50;
G06F 11/26;
Core:
more...
IPC-7:
G06F 9/455;
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| ECLA Code: |
G06F17/50C3E;
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| U.S. Class: |
Current:
703/027;
Original:
395/500.48;
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| Field of Search: |
395/500
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| Priority Number: |
| 1997-03-03 |
US1997000805852 |
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| Abstract: |
A time-sliced hardware-based emulator including at least one of: programmable I/O assignment; programmable levels of DC voltage; programmable pull-up or pull-down resistors in the emulator on a pin-by pin basis; programmable forcing and/or disabling of value output from the emulator on each pin; programmable clocking; and programmable sample modes. An emulator is connected to a target system via a Pod System Interface (PSI), a specially designed cable, and a Pod User Interface (PUI). For data traveling from the emulator to the target system, each PSI receives up to 128 bits of data from the emulator. The cable, however, is only 32 bits wide. Therefore, the emulator multiplexes the data sent over the cable, sending eight interleaved groups of 32 bits to the PSI in accordance with a fast clock signal. Each PUI receives the groups of 32 bits from the PSI and sends them to the target system in accordance with control signals from the emulator. For data traveling from the target system to the emulator, each PUI receives up to 128 bits of data from the target system. Each PUI sends four groups of 32 bits in accordance with a fast clock signal. Each PSI receives the groups of 32 bits and holds them in an internal register, sending the received bits to the emulator under control of the emulator.
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| Attorney, Agent or Firm: |
Lyon & Lyon LLP ;
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| Primary / Asst. Examiners: |
Teska, Kevin J.; Mohamed, Ayni
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| INPADOC Legal Status: |
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| Parent Case: |
RELATED APPLICATIONS
This application is related to the following applications, which are herein incorporated by reference
1. U.S. application Ser. No. 08/197,430, entitled "Method and Apparatus for a Trace Buffer in an Emulation System," of Kuijsten, filed Feb. 16, 1994and now U.S. Pat. No. 5,680,583;
2. U.S. application Ser. No. 08/242,164, entitled "Emulation System Having Multiple Emulator Clock Cycles Per Emulated Clock Cycle," of Kuijsten, filed May 13, 1994 and now abandoned;
3. U.S. application Ser. No. 08/496,239, entitled "Emulation System Having Multiple Emulated Clock Cycles Per Emulated Clock Cycle and Improved Signal Routing," of Chilton et al., filed Jun. 28, 1995; and
4. U.S. application Ser. No. 08/597,197, entitled "System and Method for Emulating Memory," of Chilton et al., filed Feb, 6, 1996 and now U.S. Pat. No. 5,819,065.
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| Family: |
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First Claim:
Show all 5 claims |
What is claimed is:
1. A target I/O system for coupling an emulator having a plurality of data bits to a target system, comprising:
- a plurality of PSI modules coupled to the emulator, each PSI module sending input bits to the emulator and receiving output bits and output enable bits from the emulator in a predetermined order;
- a cable coupled to each of the PSI modules; and
- a plurality of PUI modules, each of the PUI modules connected to a respective one of the PSI modules through a respective cable, and further coupled to the target system to transmit the input, output and output enable bits to and from target system in the predetermined order, wherein the output bits and the enable bits are sent from the emulator during different times slices.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 12 U.S. patent(s) that reference this one
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