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 Title: |
US5970110:
Precise, low-jitter fractional divider using counter of rotating clock phases
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Li, Hung-Sung; Santa Clara, CA
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| Assignee: |
NeoMagic Corp., Santa Clara, CA
other patents from NEOMAGIC CORP. (719584) (approx. 58)
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| Published / Filed: |
1999-10-19
/ 1998-01-09
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| Application Number: |
US1998000004933
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| IPC Code: |
Advanced:
G06F 7/68;
H03K 5/00;
H03K 23/68;
H03L 7/081;
H03L 7/099;
H03L 7/18;
H03L 7/197;
Core:
G06F 7/60;
H03K 23/00;
H03L 7/16;
more...
IPC-7:
H03K 21/00;
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| ECLA Code: |
G06F7/68; H03K5/00C; H03K23/68; H03L7/081; H03L7/099C; H03L7/18;
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| U.S. Class: |
Current:
377/048;
327/115;
327/147;
327/149;
327/150;
327/151;
327/232;
327/236;
327/241;
327/243;
Original:
377/048;
327/115;
327/147;
327/149;
327/150;
327/151;
327/232;
327/236;
327/241;
327/243;
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| Field of Search: |
377/048
327/115,147,149,150-1,156,158-60,232,236,241,243
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| Priority Number: |
| 1998-01-09 |
US1998000004933 |
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| Abstract: |
A fractional divider divides an input by a non-whole number M.N, where M is the integer part and N is the fractional part of the divisor. A delay line generates a group of multi-phase clocks from an input clock. A mux selects one of the multi-phase clocks as a selected clock. The selected clock increments a counter that counts to the integer part M. The selected clock also increments a rotational state machine. The rotational state machine makes the mux select a different one of the multi-phase clocks for the first N clocks so that the phase of the selected clock is rotated for N cycles. When multi-phase clocks having slightly higher delays are chosen, the selected clock's period increases, adding a fraction. When multi-phase clocks having slightly smaller delays are chosen, the selected clock's period is reduced, effectively subtracting a fraction. The delay line is part of a delay-locked loop that compares the phase of the last multi-phase clock to the input clock. Any phase difference charges a loop filter and changes an adjustment voltage. The adjustment voltage changes the delays in the delay line so that the sum of all delays in the delay line matches the clock period. Since smaller count values can be used when fractional rather than whole-number divisors are used, phase comparisons in a PLL are increased, reducing jitter and smoothing the output.
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| Attorney, Agent or Firm: |
Auvinen, Stuart T. ;
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| Primary / Asst. Examiners: |
Wambach, Margaret R.;
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| INPADOC Legal Status: |
Show legal status actions
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| Family: |
None
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First Claim:
Show all 19 claims |
I claim:
1. A fractional divider comprising:
- an input clock having an input period;
- a delay line, coupled to the input clock, having a plurality of output taps, successive output taps having successively larger phase shifts of the input clock;
- a phase mux, coupled to the plurality of output taps of the delay line, for outputting a selected clock in response to a control input;
- a rotational state machine having a plurality of states in a loop order, coupled to increment state to a next adjacent state in the loop order in response to the selected clock, the rotational state machine coupled to output a current state as the control input to the phase mux;
- wherein successive states in the loop order select successive output taps having successively larger phase shifts; and
- a counter, coupled to the selected clock, for pulsing an output clock after M pulses of the selected clock;
- wherein the rotational state machine increments to a next state, causing the phase mux to select an output tap having a larger phase shift, increasing a period of the selected clock for a first N periods of the selected clock;
- wherein the first N periods of the selected clock have an increased period while a remaining M-N periods have the input period of the input clock,
- whereby the output clock is pulsed after M.N periods of the input clock.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 50 U.S. patent(s) that reference this one
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