High density gate array cell architecture with sharing of well taps between cells (US5977574)

a first device including a first channel diffusion area and at least a first transistor gate electrode, the first device having an inner region that is interior within the gate cell and an outer region adjacent a first gate cell border;

a second device including a second channel diffusion area and at least a second transistor gate electrode, the second device having an inner region that is interior within the gate cell and an outer region adjacent a second gate cell border, the inner regions of the first and second devices adjacent to each other;

a first well tap at the outer region of the first device; and

a second well tap at the outer region of the second device;

wherein the gate cell shares the first well trap with a first adjacent gate cell in the array of gate cells and the second well tap with a second adjacent gate cell in the array of gate cells, with both said first and second devices being generally longitudinally aligned with said first and second adjacent gate cells, and with both said first and second devices being located intermediate said first and second adjacent gate cells.

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Forward References:

Show 9 U.S. patent(s) that reference this one

U.S. References:

Go to Result Set: All U.S. references | Forward references (9) | Backward references (30) | Citation Link

Patent	Pub.Date	Inventor	Assignee	Title
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US5384472	1995-01	Yin	Aspec Technology, Inc.	Symmetrical multi-layer metal logic array with continuous substrate taps and extension portions for increased gate density
US5399517	1995-03	Ashtaputre et al.	VLSI Technology, Inc.	Method of routing three layer metal gate arrays using a channel router
US5404034	1995-04	Yin	Aspec Technology, Inc.	Symmetrical multi-layer metal logic array with continuous substrate taps
US5420447	1995-05	Waggoner	SGS-Thomson Microelectronics, Inc.	Double buffer base gate array cell
US5444276	1995-08	Yokota et al.	Mitsubishi Denki Kabushiki Kaisha	Semiconductor integrated circuit macro cells with wide lines
US5452245	1995-09	Hickman et al.	Motorola, Inc.	Memory efficient gate array cell
US5473195	1995-12	Koike	NEC Corporation	Semiconductor integrated circuit device having parallel signal wirings variable in either width or interval
US5493135	1996-02	Yin	Aspec Technology, Inc.	Symmetrical multi-layer metal logic array with continuous substrate taps and extension portions for increased gate density
US5581202	1996-12	Yano et al.	Hitachi, Ltd.	Semiconductor integrated circuit device and production method thereof
US5612553	1997-03	Arakawa	Mitsubishi Denki Kabushiki Kaisha	Semiconductor integrated circuit and method of fabricating same and method of arranging cells
US5631478	1997-05	Okumura	NEC Corporation	Semiconductor integrated circuits with specific pitch multilevel interconnections

Foreign References:

Buy PDF	Publication	Date	IPC Code	Assignee	Title
	EP0782188A2	1997-07	H01L 23/52	LSI LOGIC CORPORATION	High density gate array cell architecture

Other Abstract Info:

DERABS G1998-498217

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