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 Title: |
US6006025:
Method of clock routing for semiconductor chips
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Cook, Peter William; Mount Kisco, NY
Restle, Phillip John; Katonah, NY
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| Assignee: |
International Business Machines Corporation, Armonk, NY
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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| Published / Filed: |
1999-12-21
/ 1997-09-22
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| Application Number: |
US1997000934995
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| IPC Code: |
Advanced:
G06F 1/10;
G06F 17/50;
IPC-7:
G06F 15/00;
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| ECLA Code: |
G06F1/10; G06F17/50L2; S06F217/62;
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| U.S. Class: |
Current:
716/113;
713/503;
716/130;
716/134;
Original:
395/500.15;
713/503;
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| Field of Search: |
713/503
364/488-491
395/500.13-500.15
438/129
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| Priority Number: |
| 1997-09-22 |
US1997000934995 |
| 1996-12-03 |
US1996000032216P |
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| Abstract: |
A method of wire routing includes the steps of providing an array of cells on a semiconductor chip, determining a minimum distance location between a first clock point, an second clock point and a drive point for connecting to a connection point in the array of cells, and defining a wire path through an array of blockages disposed in the array of cells from the minimum distance location to the first clock point and from the minimum distance location to the second clock point to create a path for a wire for connecting the first clock point and the second clock point to a connection point such that skew is minimized between the starting clock point and the second clock point from the connection point when a clock signal is provided to the connection point from the drive point.
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| Attorney, Agent or Firm: |
F. Chau & Associates, LLP ;
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| Primary / Asst. Examiners: |
Heckler, Thomas M.;
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| Maintenance Status: |
E2 Expired Check current status
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| INPADOC Legal Status: |
Show legal status actions
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| Parent Case: |
CROSS REFERENCE TO RELATED APPLICATION
This application claims priority to Provisional Application Ser. No. 60/032,216 filed Dec. 3, 1996. Provisional Application Ser. No. 60/032,216 is incorporated herein by reference.
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| Family: |
None
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First Claim:
Show all 15 claims |
What is claimed is:
1. A method of wire routing comprising the steps of:
- providing an array of cells on a semiconductor chip;
- determining a minimum distance location between a first clock point, a second clock point and a drive point for connecting to a connection point in the array of cells; and
- defining a wire path through an array of blockages disposed in the array of cells from the minimum distance location to the first clock point and from the minimum distance location to the second clock point to create the wire path for a wire for connecting the first clock point and the second clock point to the connection point such that skew is minimized between the first clock point and the second clock point from the connection point when a clock signal is provided at the connection point from the drive point.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 34 U.S. patent(s) that reference this one
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