Work Files Saved Searches
   My Account                                                  Search:   Quick/Number   Boolean   Advanced       Help   


 The Delphion Integrated View

  Buy Now:   Buy PDF- 17pp  PDF  |   File History  |   Other choices   
  Tools:  Citation Link  |  Add to Work File:    
  View:  Expand Details   |  INPADOC   |  Jump to: 
 
 Email this to a friend  Email this to a friend 
       
Title: US6006025: Method of clock routing for semiconductor chips
[ Derwent Title ]


Country: US United States of America

View Images High
Resolution

 Low
 Resolution

 
17 pages

 
Inventor: Cook, Peter William; Mount Kisco, NY
Restle, Phillip John; Katonah, NY

Assignee: International Business Machines Corporation, Armonk, NY
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
 News, Profiles, Stocks and More about this company

Published / Filed: 1999-12-21 / 1997-09-22

Application Number: US1997000934995

IPC Code: Advanced: G06F 1/10; G06F 17/50;
IPC-7: G06F 15/00;

ECLA Code: G06F1/10; G06F17/50L2; S06F217/62;

U.S. Class: Current: 716/113; 713/503; 716/130; 716/134;
Original: 395/500.15; 713/503;

Field of Search: 713/503 364/488-491 395/500.13-500.15 438/129

Priority Number:
1997-09-22  US1997000934995
1996-12-03  US1996000032216P

Abstract:     A method of wire routing includes the steps of providing an array of cells on a semiconductor chip, determining a minimum distance location between a first clock point, an second clock point and a drive point for connecting to a connection point in the array of cells, and defining a wire path through an array of blockages disposed in the array of cells from the minimum distance location to the first clock point and from the minimum distance location to the second clock point to create a path for a wire for connecting the first clock point and the second clock point to a connection point such that skew is minimized between the starting clock point and the second clock point from the connection point when a clock signal is provided to the connection point from the drive point.

Attorney, Agent or Firm: F. Chau & Associates, LLP ;

Primary / Asst. Examiners: Heckler, Thomas M.;

Maintenance Status: E2 Expired  Check current status

INPADOC Legal Status: Show legal status actions

Parent Case:

CROSS REFERENCE TO RELATED APPLICATION
    This application claims priority to Provisional Application Ser. No. 60/032,216 filed Dec. 3, 1996. Provisional Application Ser. No. 60/032,216 is incorporated herein by reference.

Family: None

First Claim:
Show all 15 claims
What is claimed is:     1. A method of wire routing comprising the steps of:
  • providing an array of cells on a semiconductor chip;
  • determining a minimum distance location between a first clock point, a second clock point and a drive point for connecting to a connection point in the array of cells; and
  • defining a wire path through an array of blockages disposed in the array of cells from the minimum distance location to the first clock point and from the minimum distance location to the second clock point to create the wire path for a wire for connecting the first clock point and the second clock point to the connection point such that skew is minimized between the first clock point and the second clock point from the connection point when a clock signal is provided at the connection point from the drive point.


Background / Summary: Show background / summary

Drawing Descriptions: Show drawing descriptions

Description: Show description

Forward References: Show 35 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (35)   |   Backward references (4)   |   Citation Link

Buy
PDF
Patent  Pub.Date  Inventor Assignee   Title
Get PDF - 27pp US5410491  1995-04 Minami  Kabushiki Kaisha Toshiba Method for distributing a clock signal within a semiconductor integrated circuit by minimizing clock skew
Get PDF - 28pp US5784600  1999-07 Doreswamy et al.  Sun Microsystems, Inc. Method of generating exact-length wires for routing critical signals
Get PDF - 13pp US5838581  1998-11 Kuroda  NEC Corporation Layout system for logic circuit
Get PDF - 22pp US5849610  1998-12 Zlu  Intel Corporation Method for constructing a planar equal path length clock tree
       
Foreign References: None

Other Abstract Info: DERABS G2000-105150 DERABS G2000-105150

Inquire Regarding Licensing

Powered by Verity


Plaques from Patent Awards      Gallery of Obscure PatentsNominate this for the Gallery...

Thomson Reuters Copyright © 1997-2014 Thomson Reuters 
Subscriptions  |  Web Seminars  |  Privacy  |  Terms & Conditions  |  Site Map  |  Contact Us  |  Help