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 Title: |
US6016531:
Apparatus for performing real time caching utilizing an execution quantization timer and an interrupt controller
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Rixner, Scott W.; Cambridge, MA
Ogilvie, Clarence R.; Huntington, VT
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| Assignee: |
International Business Machines Corporation, Armonk, NY
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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| Published / Filed: |
2000-01-18
/ 1995-05-26
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| Application Number: |
US1995000451802
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| IPC Code: |
Advanced:
G06F 12/08;
Core:
more...
IPC-7:
G06F 13/00;
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| ECLA Code: |
G06F12/08B; G06F12/08B6M;
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| U.S. Class: |
Current:
711/118;
710/260;
711/122;
711/131;
711/158;
711/E12.017;
711/E12.045;
Original:
711/118;
711/131;
711/158;
711/122;
710/260;
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| Field of Search: |
395/445,650,733,735,736,672
711/118,131,158,122
710/260,263,203,264,107
709/102
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| Priority Number: |
| 1995-05-26 |
US1995000451802 |
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| Abstract: |
A system for managing the flow of real time data streams into a data system cache memory is disclosed. The data system includes a central processing unit or micro controller, with a cache memory, which operates at a relatively fast operating speed, near that of the central processing unit. An interrupt controller is provided as well as a quantization timer that disables the interrupts to the CPU during an execution quantization (EQ) period, and allows the interrupts to pass at an EQ boundary. In operation, the quantization timer controls interrupts to occur only when cache load actions are at a specific quantized time, thus ensuring that a given task in the cache will execute or load for a given quantized length of time, and therefore, the possibility of loading a cache randomly only to execute a few instructions is eliminated.
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| Attorney, Agent or Firm: |
Walsh, Robert A. ;
Dillon, Andrew J. ;
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| Primary / Asst. Examiners: |
Chan, Eddie P.; Kim, Hong
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| Maintenance Status: |
E2 Expired Check current status
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| INPADOC Legal Status: |
Show legal status actions
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| Family: |
None
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First Claim:
Show all 9 claims |
We claim:
1. A data processing system comprising:
- a central processing unit;
- a multi-port cache array coupled to said central processing unit;
- a cache loader, coupled to said multi-port cache array;
- a main memory unit, comparatively slow to said cache array, coupled to said cache loader;
- a plurality of asynchronous clock interrupts, coupled to said central processing unit;
- an interrupt controller, coupled to said central processing unit, for managing real time data streams into said cache array;
- an execution quantizer coupled to said interrupt controller, wherein said execution quantizer limits any interrupts on said central processing unit from said plurality of asynchronous clock interrupts from executing after a fixed execution quantization (EQ) time; and
- gating logic, coupled to said execution quantizer, for gating off any interrupts received during a cache load or cache unload operation of a quantized block so as to allow said interrupts to be processed after completion of said cache load or unload operation.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 3 U.S. patent(s) that reference this one
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