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Title: US6034882: Vertically stacked field programmable nonvolatile memory and method of fabrication
[ Derwent Title ]


Country: US United States of America

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38 pages

 
Inventor: Johnson, Mark G.; Los Altos, CA
Lee, Thomas H.; Cupertino, CA
Subramanian, Vivek; Menlo Park, CA
Farmwald, Paul Michael; Portola Valley, CA
Cleeves, James M.; Redwood City, CA

Assignee: Matrix Semiconductor, Inc., Menlo Park, CA
other patents from MATRIX SEMICONDUCTOR, INC. (765549) (approx. 49)
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Published / Filed: 2000-03-07 / 1998-11-16

Application Number: US1998000192883

IPC Code: Advanced: G11C 11/56; G11C 17/16; H01L 27/10; H01L 27/102;
Core: G11C 17/14; more...
IPC-7: G11C 17/00;

ECLA Code: H01L27/102D; G11C11/56R; G11C17/16;

U.S. Class: Current: 365/103; 257/E27.073; 365/051; 365/063; 365/175; 365/242;
Original: 365/103; 365/063; 365/051; 365/175; 365/242;

Field of Search: 257/316 438/258 365/145,105,115,104,51,208,175,103,63

Priority Number:
1998-11-16  US1998000192883

Abstract:     A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Attorney, Agent or Firm: Blakely, Sokoloff, Taylor & Zafman LLP ;

Primary / Asst. Examiners: Nelms, David; Le, Thong

INPADOC Legal Status: Show legal status actions          Buy Now: Family Legal Status Report

Designated Country: AE AL AM AP AT AZ BA BB BG BR BY CA CH CU CZ DK EA EE ES FI GD GE GH GM HR HU ID IL IN IS KE KG KP  DE FR GB 

Family: Show 36 known family members

First Claim:
Show all 38 claims
We claim:     1. A memory cell comprising:
  • a first conductor having a first width;
  • a second conductor having a second width;
  • a steering element for providing enhanced current flow in one direction through the steering element having a first end surface with first opposite edges spaced-apart by a distance equal to the first width and second opposite edges spaced-apart by a distance equal to the second width where the first opposite edges are aligned with the first conductor and where the first end surface is in continuous contact with the first conductor;
  • a state change element for retaining a programmed state, connected in series with the steering element having a second end surface with third opposite edges spaced-apart by a distance equal to the first width and fourth opposite edges spaced-apart by a distance equal to the second width where the fourth opposite edges are aligned with the second conductor and where the second end surface is in continuous contact with the second conductor, and;
  • the steering element and state change element being vertically aligned with one another.


Background / Summary: Show background / summary

Drawing Descriptions: Show drawing descriptions

Description: Show description

Forward References: Show 396 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (396)   |   Backward references (42)   |   Citation Link

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Patent  Pub.Date  Inventor Assignee   Title
  US3576549  1971-04 Hess et al.  Cogar Corporation SEMICONDUCTOR DEVICE, METHOD, AND MEMORY ARRAY
Buy PDF- 5pp US3582908  1971-06 Koo et al.  Bell Telephone Laboratories, Incorporated WRITING A READ-ONLY MEMORY WHILE PROTECTING NONSELECTED ELEMENTS
Buy PDF- 8pp US3634929  1972-01 Yoshida et al.  Tokyo Shibaura Electric Co., Ltd. METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUITS
Buy PDF- 7pp US3671948  1972-06 Cassen et al.  North American Rockwell Corporation READ-ONLY MEMORY
Buy PDF- 8pp US3717852  1973-02 Abbas et al.  International Business Machines Corporation ELECTRONICALLY REWRITABLE READ-ONLY MEMORY USING VIA CONNECTIONS
  US3728695  1973-04 Frohman-Bentchkowsky  Intel Corporation RANDOM-ACCESS FLOATING GATE MOS MEMORY ARRAY
Buy PDF- 7pp US3787822  1974-01 Rioult  U.S. Philips Corporation METHOD OF PROVIDING INTERNAL CONNECTIONS IN A SEMICONDUCTOR DEVICE
Buy PDF- 14pp US3863231  1975-01 Taylor  National Research Development Corporation READ ONLY MEMORY WITH ANNULAR FUSE LINKS
Buy PDF- 13pp US3990098  1976-11 Mastrangelo  E. I. Du Pont de Nemours and Co. Structure capable of forming a diode and associated conductive path
Buy PDF- 15pp US4146902  1979-03 Tanimoto et al.  Nippon Telegraph and Telephone Public Corp. Irreversible semiconductor switching element and semiconductor memory device utilizing the same
Buy PDF- 8pp US4203123  1980-05 Shanks  Burroughs Corporation Thin film memory device employing amorphous semiconductor materials
Buy PDF- 13pp US4203158  1980-05 Frohman-Bentchkowsky et al.  Intel Corporation Electrically programmable and erasable MOS floating gate memory device employing tunneling and method of fabricating same
Buy PDF- 10pp US4281397  1981-07 Neal et al.  Texas Instruments Incorporated Virtual ground MOS EPROM or ROM matrix
Buy PDF- 12pp US4419741  1983-12 Stewart et al.  RCA Corporation Read only memory (ROM) having high density memory array with on pitch decoder circuitry
Buy PDF- 8pp US4420766  1983-12 Kasten  Harris Corporation Reversibly programmable polycrystalline silicon memory element
Buy PDF- 17pp US4442507  1984-04 Roesner  Burroughs Corporation Electrically programmable read-only memory stacked above a semiconductor substrate
Buy PDF- 10pp US4494135  1985-01 Moussie  U.S. Philips Corporation Programmable read only memory cell having an electrically destructible programmation element integrally formed with a junction diode
Buy PDF- 16pp US4499557  1985-02 Holmberg et al.  Energy Conversion Devices, Inc. Programmable cell for use in programmable electronic arrays
Buy PDF- 13pp US4507757  1985-03 McElroy  Texas Instruments Incorporated Avalanche fuse element in programmable memory
Buy PDF- 5pp US4543594  1985-09 Mohsen et al.  Intel Corporation Fusible link employing capacitor structure
Buy PDF- 8pp US4569121  1986-02 Lim et al.  Signetics Corporation Method of fabricating a programmable read-only memory cell incorporating an antifuse utilizing deposition of amorphous semiconductor layer
Buy PDF- 28pp US4646266  1987-02 Ovshinsky et al.  Energy Conversion Devices, Inc. Programmable semiconductor structures and methods for using the same
Buy PDF- 9pp US4820657  1989-04 Hughes et al.  Georgia Tech Research Corporation Method for altering characteristics of junction semiconductor devices
Buy PDF- 11pp US4823181  1989-04 Mohsen et al.  Actel Corporation Programmable low impedance anti-fuse element
Buy PDF- 12pp US4876220  1989-10 Mohsen et al.  Actel Corporation Method of making programmable low impedance interconnect diode element
Buy PDF- 12pp US4881114  1989-11 Mohsen et al.  Actel Corporation Selectively formable vertical diode circuit element
Buy PDF- 14pp US4899205  1990-02 Hamdy et al.  Actel Corporation Electrically-programmable low-impedance anti-fuse element
Buy PDF- 12pp US4922319  1990-05 Fukushima  Fujitsu Limited Semiconductor programmable memory device
Buy PDF- 9pp US4943538  1990-07 Mohsen et al.  Actel Corporation Programmable low impedance anti-fuse element
Buy PDF- 5pp US5070383  1991-12 Sinar et al.  Zoran Corporation Programmable memory matrix employing voltage-variable resistors
Buy PDF- 33pp US5311039  1994-05 Kimura et al.  Seiko Epson Corporation PROM and ROM memory cells
Buy PDF- 13pp US5334880  1994-08 Abadeer et al.  International Business Machines Corporation Low voltage programmable storage element
Buy PDF- 11pp US5391518  1995-02 Bhushan  VLSI Technology, Inc. Method of making a field programmable read only memory (ROM) cell using an amorphous silicon fuse with buried contact polysilicon and metal electrodes
Buy PDF- 10pp US5441907  1995-08 Sung et al.  Taiwan Semiconductor Manufacturing Company Process for manufacturing a plug-diode mask ROM
Buy PDF- 9pp US5463244  1995-10 De Araujo et al.  Symetrix Corporation Antifuse programmable element using ferroelectric material
Buy PDF- 8pp US5536968  1996-07 Crafts et al.  AT&T Global Information Solutions Company Polysilicon fuse array structure for integrated circuits
Buy PDF- 9pp US5675547  1997-10 Koga  Sony Corporation One time programmable read only memory programmed by destruction of insulating layer
Buy PDF- 6pp US5737259  1998-04 Chang  United Microelectronics Corporation Method of decoding a diode type read only memory
Buy PDF- 13pp US5751012  1998-05 Wolstenholme et al.  Micron Technology, Inc. Polysilicon pillar diode for use in a non-volatile memory cell
Buy PDF- 22pp US5776810  1998-07 Guterman et al.  Sandisk Corporation Method for forming EEPROM with split gate source side injection
Buy PDF- 23pp US5835396  1998-11 Zhang   Three-dimensional read-only memory
Buy PDF- 42pp US5883409  1999-03 Guterman et al.  Sandisk Corporation EEPROM with split gate source side injection
       
Foreign References: None

Other Abstract Info: DERABS C2000-246114

Other References:
  • A New Programmable Cell Utilizing Insulator Breakdown, 1985, pp. 640-IEDM-85 (26.7), pp. IEDM 85-641 (26.7), 642-IEDM (26.7), IEMD Technical Digest "International Electron Devices Meeting 1985".
  • Solid State Circuits, "A Fully Decoded 2048-Bit Elctrically Programmable FAMOS Read-Only Memory", "A Memory System Based On Surface-Charge Transport".


  • Continuity Data:
    Application Number Filed Notes

    US1998000192883 1998-11-16  is a related to the prior publication
         US20030016553A1 issued 2003-01-23  Vertically stacked field programmable nonvolatile memory and method of fabrication

    US1998000192883 1998-11-16  is a related to the prior publication
         US20030206429A2 issued 2003-11-06  VERTICALLY STACKED FIELD PROGRAMMABLE NONVOLATILE MEMORY AND METHOD OF FABRICATION

    US1998000192883 1998-11-16  is a related to the prior publication
         US20050063220A1 issued 2005-03-24  Memory device and method for simultaneously programming and/or reading memory cells on different levels

    US1998000192883 1998-11-16  is a related to the prior publication
         US20050105371A1 issued 2005-05-19  Integrated circuit incorporating three-dimensional memory array with dual opposing decoder arrangement

    US1998000192883 1998-11-16  is a related to the prior publication
         US20060134837A1 issued 2006-06-22  Vertically stacked field programmable nonvolatile memory and method of fabrication

    US1998000192883 1998-11-16  is a related to the prior publication
         US20060141679A1 issued 2006-06-29  Vertically stacked field programmable nonvolatile memory and method of fabrication

    11925723   is a continuation of
    US2006000355214  2006-02-14
         US7319053 issued 2008-01-15   Vertically stacked field programmable nonvolatile memory and method of fabrication

    US2005000987091   is a continuation of
    US2004000774818  2004-02-09   (pending) [presumed granted]
         US7190602 issued 2007-03-13   Integrated circuit incorporating three-dimensional memory array with dual opposing decoder arrangement

    US2004000987091 2004-11-12  is a continuation of
    US2004000774818  2004-02-09   (pending) [presumed granted]
         US7190602 issued 2007-03-13   Integrated circuit incorporating three-dimensional memory array with dual opposing decoder arrangement

    US2004000774818 2004-02-09  is a continuation of
    US2002000253354  2002-09-23   (granted)
         US6780711 issued 2004-08-24   Vertically stacked field programmable nonvolatile memory and method of fabrication

    US2004000774818   is a continuation of
    US2002000253354  2002-09-23
         US6780711 issued 2004-08-24   Vertically stacked field programmable nonvolatile memory and method of fabrication

    US2006000355214 2006-02-14  is a continuation of
    US2001000939498  2001-08-24   (pending) [presumed granted]
         US7157314 issued 2007-01-02   Vertically stacked field programmable nonvolatile memory and method of fabrication

    US2006000354470 2006-02-14  is a continuation of
    US2001000939498  2001-08-24   (pending) [presumed granted]
         US7157314 issued 2007-01-02   Vertically stacked field programmable nonvolatile memory and method of fabrication

    US2002000251206 2002-09-19  is a division of
    US2001000939498  2001-08-24   (pending) [presumed granted]
         US7157314 issued 2007-01-02   Vertically stacked field programmable nonvolatile memory and method of fabrication

    US2002000251206   is a division of
    US2001000939498  2001-08-24   (pending) [presumed granted]
         US7157314 issued 2007-01-02   Vertically stacked field programmable nonvolatile memory and method of fabrication

    11355214   is a continuation of
    US2001000939498  2001-08-24
         US7157314 issued 2007-01-02   Vertically stacked field programmable nonvolatile memory and method of fabrication

    11354470   is a continuation of
    US2001000939498  2001-08-24
         US7157314 issued 2007-01-02   Vertically stacked field programmable nonvolatile memory and method of fabrication

    US2002000253354 2002-09-23  is a continuation of
    US2001000939431  2001-08-24   (granted)
         US6483736 issued 2002-11-19   Vertically stacked field programmable nonvolatile memory and method of fabrication

    US2002000253354   is a continuation of
    US2001000939431  2001-08-24
         US6483736 issued 2002-11-19   Vertically stacked field programmable nonvolatile memory and method of fabrication

    US2001000939498 2001-08-24  is a continuation of
    US2000000714440  2000-11-15   (pending) [presumed granted]
         US6351406 issued 2002-02-26   Vertically stacked field programmable nonvolatile memory and method of fabrication

    US2001000939498 2001-08-24  is a continuation of
    US2000000714440  2000-11-15   (granted)
         US6351406 issued 2002-02-26   Vertically stacked field programmable nonvolatile memory and method of fabrication

    US2001000939498   is a continuation of
    US2000000714440  2000-11-15
         US6351406 issued 2002-02-26   Vertically stacked field programmable nonvolatile memory and method of fabrication

    US2001000939498 2001-08-24  is a continuation of
    US2000000714440  2000-11-15   (granted)
         6,351,406 issued

    US2001000939431 2001-08-24  is a continuation of
    US2000000714440  2000-11-15   (pending) [presumed granted]
         US6351406 issued 2002-02-26   Vertically stacked field programmable nonvolatile memory and method of fabrication

    US2001000939431 2001-08-24  is a continuation of
    US2000000714440  2000-11-15   (granted)
         US6351406 issued 2002-02-26   Vertically stacked field programmable nonvolatile memory and method of fabrication

    US2001000939431   is a continuation of
    US2000000714440  2000-11-15
         US6351406 issued 2002-02-26   Vertically stacked field programmable nonvolatile memory and method of fabrication

    US2000000714440 2000-11-15  is a continuation of
    US1999000469658  1999-12-22   (granted)
         US6185122 issued 2001-02-06   Vertically stacked field programmable nonvolatile memory and method of fabrication

    US2000000714440   is a continuation of
    US1999000469658  1999-12-22
         US6185122 issued 2001-02-06   Vertically stacked field programmable nonvolatile memory and method of fabrication

    US2000000714440 2000-11-15  is a continuation of
    US1999000469658  1999-12-22   (granted)
         6,185,122 issued

    US1999000469658 1999-12-22  is a division of
    >US1998000192883<  1998-11-16   (granted)
         US6034882 issued 2000-03-07   Vertically stacked field programmable nonvolatile memory and method of fabrication

    US1999000469658   is a division of
    >US1998000192883<  1998-11-16
         US6034882 issued 2000-03-07   Vertically stacked field programmable nonvolatile memory and method of fabrication

    US1999000469658 1999-12-22  is a division of
    >US1998000192883<  1998-11-16   (granted)
         6,34,882 issued


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