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 Title: |
US6065033:
Wallace-tree multipliers using half and full adders
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Jouppi, Norman P.; Palo Alto, CA
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| Assignee: |
Digital Equipment Corporation, Maynard, MA
other patents from DIGITAL EQUIPMENT CORPORATION (147695) (approx. 2,345)
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| Published / Filed: |
2000-05-16
/ 1997-02-28
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| Application Number: |
US1997000808070
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| IPC Code: |
Advanced:
G06F 7/52;
G06F 7/527;
G06F 7/53;
Core:
G06F 7/48;
IPC-7:
G06F 7/50;
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| ECLA Code: |
G06F7/53B;
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| U.S. Class: |
708/670;
708/625;
708/708;
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| Field of Search: |
364/768,787.01,786.03,754.01,760.02,757
395/800
235/175
708/670,626,625,708
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| Priority Number: |
| 1997-02-28 |
US1997000808070 |
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| Abstract: |
An apparatus sums a plurality of columns of binary bits to produce a plurality of partial sum and carry bits. The bits of a particular column being of the same order of magnitude, and the bits of different columns differing in orders of magnitude. The apparatus includes one or more full adder. Each full adder receives three bits as an input to produce a first sum bit and a first carry bit as output. The apparatus also includes one or more half adders. Each half adder receives two bits as input to produce a second sum bit and a second carry bit as output. The full adders and half adder are interconnected as a plurality of interconnecting column adders. Each column adder sums bits of the input of at least one column and generates a partial sum and carry bit. Each column adder has a plurality of stages. A plurality of conductors interconnect the stages of each column adder with other stages in the same column adder and with stages in other adjacent column adders.
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| Attorney, Agent or Firm: |
Pennie & Edmonds LLP ;
Brinkman, Dirk ;
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| Primary / Asst. Examiners: |
Ngo, Chuong Dinh; Nguyen, Nguyen
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| INPADOC Legal Status: |
Show legal status actions
Family Legal Status Report
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| Designated Country: |
AT BE CH DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE DE FR GB
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| Family: |
Show 5 known family members
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First Claim:
Show all 11 claims |
What is claimed is:
1. An apparatus for summing a plurality of columns of binary bits to produce a plurality of partial sum and carry bits, the bits of a particular column being of the same orders of magnitude and the bits of different columns differing in order of magnitude, comprising:
- a full adder, the full adder receiving three bits of the particular column as first input to produce a first sum bit and a first carry bit as output;
- a half adder receiving two bits of the particular column as second input to produce a second sum bit and a second carry bit as output, the half and full adders being configured as a plurality of interconnecting column adders, each column adder summing bits of the input of at least one column and generating a partial sum and carry bit, each column adder having a plurality of stages; and
- a plurality of conductors for interconnecting the stages of each column adder with other stages in the same column adder and with stages in other column adders,
- wherein the half adder is used in the particular column when the particular column has two remainder bits after dividing the number of bits in the particular column by three, and an adjacent column having bits with a lower order of magnitude has more bits than the particular column.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 2 U.S. patent(s) that reference this one
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