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 Title: |
US6081570:
Parallel integrated frame synchronizer chip
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Ghuman, Parminder Singh; Severn, MD
Solomon, Jeffrey Michael; Menlo Park, CA
Bennett, Toby Dennis; Hyattsville, MD
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| Assignee: |
The United States of America as represented by the Administrator of the National Aeronautics and Space Administration, Washington, DC
other patents from UNITED STATES OF AMERICA, NATIONAL AERONAUTICS AND SPACE ADMINISTRATION (597260) (approx. 4,819)
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| Published / Filed: |
2000-06-27
/ 1997-09-02
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| Application Number: |
US1997000921666
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| IPC Code: |
Advanced:
H04J 3/06;
H04L 7/04;
Core:
more...
IPC-7:
H04L 7/00;
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| ECLA Code: |
H04J3/06A1;
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| U.S. Class: |
Current:
375/368;
370/514;
Original:
375/368;
370/514;
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| Field of Search: |
375/368,370
370/514,520
371/042,46
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| Government Interest: |
ORIGIN OF THE INVENTION
The invention described herein was made by employees of the United States Government and by a contractor employee in the performance of work under a NASA contract and therefore is subject to Public Law 96-517 (35 U.S.C. §200 et. seq.) and may be manufactured and used by or for the Government for governmental purposes without the payment of any royalties thereon or therefor.
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| Priority Number: |
| 1997-09-02 |
US1997000921666 |
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| Abstract: |
A parallel integrated frame synchronizer which implements a sequential pipeline process wherein serial data in the form of telemetry data or weather satellite data enters the synchronizer by means of a front-end subsystem and passes to a parallel correlator subsystem or a weather satellite data processing subsystem. When in a CCSDS mode, data from the parallel correlator subsystem passes through a window subsystem, then to a data alignment subsystem and then to a bit transition density (BTD)/cyclical redundancy check (CRC) decoding subsystem. Data from the BTD/CRC decoding subsystem or data from the weather satellite data processing subsystem is then fed to an output subsystem where it is output from a data output port.
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| Primary / Asst. Examiners: |
Ghebretinsae, Temesghen; Burd, Kevin M
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| Maintenance Status: |
E2 Expired Check current status
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| INPADOC Legal Status: |
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| Parent Case: |
CROSS REFERENCE TO RELATED APPLICATION
This application now formalizes and incorporates herein by reference Provisional Application Ser. No. 60/028,733, "Parallel Integrated Frame Synchronizer Chip", Parminder S. Ghuman et al, filed on Oct. 15, 1996, and claims the priority date thereof under 35 U.S.C. §119(e).
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| Family: |
None
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First Claim:
Show all 40 claims |
What is claimed is:
1. A parallel integrated data frame synchronizer for locating valid sync marker bit patterns between frames of data in a serial telemetry data stream and receiving clock signals from a system clock, comprising:
- (a) a front end subsystem for receiving synchronous and asynchronous input data from a plurality of input interfaces including parallel and serial interfaces;
- (b) a parallel correlation subsystem coupled to the front end subsystem and including a plurality of multi-bit data comparators for respectively determining, in parallel, an error for each successive bit position of a multi-bit data byte in the input data by comparing the byte against a data byte of an expected sync marker bit pattern, and a corresponding plurality of sync marker generators for respectively generating a valid sync mark pattern when the total number of bit errors resulting from comparing are within a predetermined error tolerance;
- (c) a window subsystem coupled to the parallel correlation subsystem for locking onto one of said valid sync marker bit patterns;
- (d) a data alignment subsystem coupled to the window subsystem for aligning bytes of data into data frames having predetermined byte boundaries following locking onto said one valid sync marker bit pattern;
- (e) a BTD/CRC subsystem coupled to the data alignment subsystem for selectively performing optional bit transition density (BTD) decoding on the serial data stream when so encoded to assist in sync marker bit pattern locking or performing cyclic redundancy check (CRC) error detection on the serial data stream for detecting errors in the serial data stream; and
- (f) an output subsystem coupled to the BTD/CRC subsystem for outputting the serial data stream for external use in byte or word format.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 15 U.S. patent(s) that reference this one
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