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 Title: |
US6100735:
Segmented dual delay-locked loop for precise variable-phase clock generation
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Lu, Crist Y.; Mission Viejo, CA
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| Assignee: |
Centillium Communications, Inc., Fremont, CA
other patents from CENTILLIUM COMMUNICATIONS, INC. (771192) (approx. 9)
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| Published / Filed: |
2000-08-08
/ 1998-11-19
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| Application Number: |
US1998000197320
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| IPC Code: |
Advanced:
H03L 7/07;
H03L 7/081;
H03L 7/089;
Core:
more...
IPC-7:
H03L 7/06;
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| ECLA Code: |
H03L7/07; H03L7/081A1;
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| U.S. Class: |
Current:
327/158;
327/161;
327/271;
327/277;
327/299;
331/025;
331/DIG.002;
375/376;
Original:
327/158;
327/161;
327/271;
327/277;
327/299;
375/376;
331/025;
331/DIG.2;
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| Field of Search: |
327/261,269-271,276,277,284,141,155-158,161,291,295,298,299
375/373,371,376
331/025,11,12,DIG. 2
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| Priority Number: |
| 1998-11-19 |
US1998000197320 |
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| Abstract: |
A segmented dual delay-locked-loop (DLL) has a coarse DLL and a fine DLL. Each DLL has a series of buffers, a phase detector, charge pump, and bias-voltage generator. The bias voltage controls the delay through the buffers. The bias voltage of the coarse DLL is adjusted by the phase comparator to lock the total delay through the buffers to be equal the input-clock period. The coarse DLL divides an input clock into M equal intervals of the input-clock period and generates M intermediate clocks having M different phases. An intermediate mux selects one of the M intermediate clocks in response to a phase-selecting address. The selected intermediate clock K and a next-following intermediate clock K+1 are both selected and applied to the fine DLL. The K clock is input to a series of N buffers in the fine DLL while the K+1 clock is directly input to a phase detector. The phase detector compares the K+1 clock to the K clock after the delay through the buffers. The bias voltage of the fine DLL is adjusted by the phase comparator to lock the total delay through the N buffers to the coarse interval between the K and K+1 intermediate clocks. Thus the input clock is divided into M intervals by the coarse DLL, then the fine DLL further divides one coarse interval into N intervals. Very fine phases are generated with only a M-buffer DLL and an N-buffer DLL.
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| Attorney, Agent or Firm: |
Auvinen, Stuart T. ;
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| Primary / Asst. Examiners: |
Callahan, Timothy P.; Nguyen, Minh
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| INPADOC Legal Status: |
Show legal status actions
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| Family: |
None
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First Claim:
Show all 20 claims |
I claim:
1. A segmented dual delay-locked-loop (DLL) comprising:
- an input clock;
- a coarse delay-locked loop (DLL), receiving the input clock, for generating a plurality of intermediate clocks each having a different phase but having a same period as the input clock, the coarse DLL having a feedback loop for adjusting phase offsets of the intermediate clocks;
- an intermediate mux, receiving the plurality of intermediate clocks, for outputting a K clock and a K+1 clock, wherein the K+1 clock has a phase immediately following a phase of the K clock;
- a fine delay-locked loop (DLL), receiving the K clock and the K+1 clock from the intermediate mux, for generating a plurality of fine clocks each having a different phase between the phase of the K clock and the phase of the K+1 clock, wherein the plurality of fine clocks all have the same period as the input clock; and
- an output mux, receiving the plurality of fine clocks from the fine DLL, for outputting a generated clock
- whereby the intermediate mux selects a coarse phase from the plurality of clocks generated by the coarse DLL, while the output mux selects a fine phase between phases of two adjacent intermediate clocks from the intermediate mux.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
Show description
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| Forward References: |
Show 89 U.S. patent(s) that reference this one
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| Foreign References: |
None
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| Other Abstract Info: |
DERABS G2000-498668
DERABS G2000-498668
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| Other References: |
Maneatis and Horowitz, "Precise Delay Generation Using Coupled Oscillators", IEEE JSSC vol. 28, No. 12, Dec. 1993, pp. 1273-1282.
(10 pages)
Cited by 14 patents
[ISI abstract]
Christiansen, "An Integrated high Resolution CMOS Timing Geneterator Based on an Array of Delay Locked Loops", IEEE JSSC vol. 31, No. 7, Jul. 1996, pp. 952-957.
(6 pages)
Cited by 59 patents
[ISI abstract]
Sidiropoulos and Horowitz, "A Semidigital Dual Delay-Locked Loop", IEEE JSSC vol. 32, No. 11, Nov. 1997, pp. 1683-1692.
(10 pages)
Cited by 57 patents
[ISI abstract]
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