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 Title: |
US6112318:
Performance counters controlled by programmable logic
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Jouppi, Norman P.; Palo Alto, CA
McCormack, Joel J.; Boulder, CO
Seiler, Larry D.; Boylston, MA
Yeager, Mark O.; West Groton, MA
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| Assignee: |
Digital Equipment Corporation, Maynard, MA
other patents from DIGITAL EQUIPMENT CORPORATION (147695) (approx. 2,345)
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| Published / Filed: |
2000-08-29
/ 1997-08-11
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| Application Number: |
US1997000909403
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| IPC Code: |
Advanced:
G06F 11/34;
Core:
more...
IPC-7:
H02H 3/05;
H03K 19/003;
H04B 1/74;
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| ECLA Code: |
G06F11/34C; G06F11/34T6;
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| U.S. Class: |
Current:
714/047;
714/039;
714/704;
714/E11.192;
714/E11.205;
Original:
714/047;
714/039;
714/704;
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| Field of Search: |
714/047,45,34,37,39,704
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| Priority Number: |
| 1997-08-11 |
US1997000909403 |
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| Abstract: |
An apparatus and method for counting event signals generated by a computer system is described. The event signals are indicative of the performance of the computer system. Programmable logic enhances the functionality of performance counters by enabling the system user to specify, during the execution of an application program, which event signals to count. The system user can dynamically configure the programmable logic to select a subset of the event signals generated by the computer system, and to combine the selected subset of event signals to generate a new event signal that can be counted. Other new event signals can be generated by the programmable logic from the selected subset of event signals. A user of the computer system can dynamically make the selection of any one of the new event signals for counting.
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| Attorney, Agent or Firm: |
Pennie & Edmonds LLP ;
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| Primary / Asst. Examiners: |
Le, Dieu-Minh T.;
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| Maintenance Status: |
CC Certificate of Correction issued
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| INPADOC Legal Status: |
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| Designated Country: |
AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE DE FR GB
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| Family: |
Show 6 known family members
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First Claim:
Show all 20 claims |
What is claimed is:
1. An apparatus for counting event signals generated by a computer system, comprising:
- an event signal selector circuit that selects a subset of at least two event signals from a set of event signals generated by the computer system, the at least two event signals being generated concurrently;
- an event signal combiner circuit including:
- a logic circuit that, in a single clock cycle, generates combined event signals based on the at least two event signals of the subset in accordance with predefined logic functions, and
- a multiplexor that receives the combined event signals from the logic circuit, and outputs one of the combined event signals as a new event signal in accordance with a selected one of the predefined logic functions; and
- a counter that is incremented in response to the new event signal.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 20 U.S. patent(s) that reference this one
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