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 Title: |
US6124741:
Accurate PLL charge pump with matched up/down currents from Vds-compensated common-gate switches
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Arcus, Christopher G.; San Jose, CA
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| Assignee: |
Pericom Semiconductor Corp., San Jose, CA
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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| Published / Filed: |
2000-09-26
/ 1999-03-08
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| Application Number: |
US1999000264284
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| IPC Code: |
Advanced:
H03K 17/687;
H03L 7/089;
Core:
more...
IPC-7:
H03K 3/00;
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| ECLA Code: |
H03K17/687B2; H03L7/089C4;
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| U.S. Class: |
Current:
327/112;
326/083;
Original:
327/112;
326/083;
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| Field of Search: |
327/108,111,112,103,434,427
329/083
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| Priority Number: |
| 1999-03-08 |
US1999000264284 |
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| Abstract: |
A more accurate charge pump reduces phase error in a PLL. An UP input pulse causes a p-channel drive transistor to charge a filter capacitor on the output, while a down DN input pulse causes an n-channel drive transistor to discharge the output. The drive transistors are connected to power or ground through a supply transistor. The supply transistor is biased on in the linear region and is not switched off. The sources of the drive transistors are always driven by the supply transistors, preventing phase error from floating sources. The drive transistors are common-gate switches with their gates biased by a compensating bias generator. The p-channel drive transistor current variations with Vds are compensated by providing a similar current variation to the n-channel drive transistor. Thus the bias is adjusted to compensate for drain-source voltage changes that can cause the up and down currents from the drive transistors to mismatch. The drive transistors are switched on and off by the up and down input pulses by current sources that steer additional current through the supply transistors. The additional current raises the n-channel drive transistor source to turn off the down current. Additional current from a current source also lowers the p-channel drive transistor's source to turn it off. The same polarity and threshold are used for both up and down input pulses, further reducing phase error.
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| Attorney, Agent or Firm: |
Auvinen, Stuart T. ;
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| Primary / Asst. Examiners: |
Kim, Jung Ho;
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| INPADOC Legal Status: |
Show legal status actions
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| Family: |
None
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First Claim:
Show all 20 claims |
I claim:
1. A charge pump comprising:
- an up input and a down input to the charge pump;
- an output having an output capacitance to be charged in response to the up input and discharged in response to the down input;
- a charging common-gate switch, coupled to the output to charge the output capacitance in response to the up input, the charging common-gate switch having a control gate coupled to an upper bias voltage, the charging common-gate switch coupled to conduct current from an upper source node to the output in response to a voltage difference between the upper bias voltage and an upper-source voltage of the upper source node;
- wherein the upper bias voltage is quasi-constant and not responsive to the up input;
- an upper supply resistor, coupled between the upper source node and a power supply, for conducting current to the upper source node;
- an upper current source, coupled to the upper source node, for drawing additional current through the upper supply resistor to lower the upper-source voltage and thereby disable the charging common-gate switch in response to an inactive state of the up input;
- a discharging common-gate switch, coupled to the output to discharge the output capacitance in response to the down input, the discharging common-gate switch having a control gate coupled to a lower bias voltage, the discharging common-gate switch coupled to conduct current from the output to a lower source node in response to a voltage difference between the lower bias voltage and a lower-source voltage of the lower source node;
- wherein the lower bias voltage is quasi-constant and not responsive to the down input;
- a lower supply resistor, coupled between the lower source node and a ground, for conducting current from the lower source node to the ground; and
- a lower current source, coupled to the lower source node, for sourcing additional current through the lower supply resistor to raise the lower-source voltage and thereby disable the discharging common-gate switch in response to an inactive state of the down input,
whereby the upper and lower current sources disable the common-gate switches by raising the lower-source voltage and reducing the upper-source voltage.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 25 U.S. patent(s) that reference this one
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