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Title: US6148387: System and method for securely utilizing basic input and output system (BIOS) services
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Country: US United States of America

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33 pages

 
Inventor: Galasso, Leonard J.; Rancho Santa Margarita, CA
Zilmer, Matthew E.; Upland, CA
Phan, Quang; Tustin, CA

Assignee: Phoenix Technologies, Ltd., San Jose, CA
other patents from PHOENIX TECHNOLOGIES LTD. (698987) (approx. 54)
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Published / Filed: 2000-11-14 / 1999-06-18

Application Number: US1999000336889

IPC Code: Advanced: G06F 9/40; G06F 9/445; G06F 9/50; G06F 12/02; G06F 12/10; G06F 21/00;
Core: G06F 9/46; more...
IPC-7: G06F 9/00;

ECLA Code: G06F9/40; G06F9/445; G06F12/02D; G06F21/00N3P;

U.S. Class: Current: 711/203; 711/006; 711/173; 711/202; 711/204; 711/205; 711/E12.005; 712/E09.082; 713/001; 713/002;
Original: 711/203; 711/006; 711/173; 711/202; 711/204; 711/205; 395/651; 395/652;

Field of Search: 711/202,203,6,173,217,220 713/002

Priority Number:
1999-06-18  US1999000336889
1997-10-09  US1997000947990

Abstract:     In accordance with one aspect of the current invention, the system comprises a memory for storing instruction sequences by which the processor-based system is processed, where the memory includes a physical memory and a virtual memory. The system also comprises a processor for executing the stored instruction sequences. The stored instruction sequences include process acts to cause the processor to: map a plurality of predetermined instruction sequences from the physical memory to the virtual memory, determine an offset to one of the plurality of predetermined instruction sequences in the virtual memory, receive an instruction to execute the one of the plurality of predetermined instruction sequences, transfer control to the one of the plurality of predetermined instruction sequences, and process the one of the plurality of predetermined instruction sequences from the virtual memory. In accordance with another aspect of the present invention, the system includes an access driver to generate a service request to utilize BIOS services such that the service request contains a service request signature created using a private key in a cryptographic key pair. The system also includes an interface to verify the service request signature using a public key in the cryptographic key pair to ensure integrity of the service request.

Attorney, Agent or Firm: Irell & Manella LLP ;

Primary / Asst. Examiners: Yoo, Do Hyun; Nguyen, Than

Maintenance Status: E1 Expired  Check current status

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Related Applications: Go to Result Set: 1 patent(s) that list this one as related
Application Number Filed Patent Pub. Date  Title
US1997000947990 1997-10-09       


       
Parent Case:

RELATED APPLICATION
    This application is a Continuation-In-Part of U.S. patent application Ser. No. 08/947,990 filed on Oct. 9, 1997, now abandoned.

Designated Country: AL AM AP AT AZ BA BB BG BR BY CA CH CU CZ DE DK EA EE EP ES FI GD GE GH GM HR HU ID IL IS KE KG KP KR KZ LC 

Family: Show 16 known family members

First Claim:
Show all 26 claims
What is claimed is:     1. A system for accessing and executing instruction sequences in a physical memory from a virtual memory in a processor-based system, comprising:
  • a memory for storing instruction sequences by which the processor-based system is processed, the memory including a physical memory and a virtual memory; and
  • a processor for executing the stored instruction sequences; and
  • wherein the stored instruction sequences cause the processor to: (a) map a plurality of BIOS instruction sequences from the physical memory to the virtual memory, said BIOS instruction sequences including a BIOS service directory; and map BIOS data from the physical memory to the virtual memory; (b) determine a starting virtual address of the BIOS service directory; and determine a starting virtual address of one of the plurality of BIOS instruction sequences by reference to the BIOS service directory; (c) receive an instruction to execute the one of said plurality of predetermined instruction sequences; (d) transfer control to the one of said plurality of predetermined instruction sequences; and (e) process the one of said plurality of predetermined instruction sequences from the virtual memory.


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Forward References: Show 46 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (46)   |   Backward references (17)   |   Citation Link

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PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 18pp US4563737  1986-01 Nakamura et al.  Hitachi, Ltd. Virtual storage management
Buy PDF- 22pp US4742447  1988-05 Duvall et al.  International Business Machines Corporation Method to control I/O accesses in a multi-tasking virtual memory virtual machine type data processing system
Buy PDF- 35pp US4868738  1989-09 Kish et al.  Lanier Business Products, Inc. Operating system independent virtual memory computer system
Buy PDF- 27pp US4926322  1990-05 Stimac et al.  Compag Computer Corporation Software emulation of bank-switched memory using a virtual DOS monitor and paged memory management
Buy PDF- 12pp US4928237  1990-05 Bealkowski et al.  International Business Machines Corp. Computer system having mode independent addressing
Buy PDF- 11pp US5133058  1992-07 Jensen  Sun Microsystems, Inc. Page-tagging translation look-aside buffer for a computer memory system
Buy PDF- 13pp US5193161  1993-03 Bealkowski et al.  International Business Machines Corp. Computer system having mode independent addressing
Buy PDF- 25pp US5212633  1993-05 Franzmeier  ShareData System for transferring resident programs to virtual area and recalling for instant excution in memory limited DOS system using program control tables
Buy PDF- 13pp US5255379  1993-10 Melo  Sun Microsystems, Inc. Method for automatically transitioning from V86 mode to protected mode in a computer system using an Intel 80386 or 80486 processor
Buy PDF- 16pp US5301287  1994-04 Herrell et al.  Hewlett-Packard Company User scheduled direct memory access using virtual addresses
Buy PDF- 8pp US5361340  1994-11 Kelly et al.  Sun Microsystems, Inc. Apparatus for maintaining consistency in a multiprocessor computer system using virtual caching
Buy PDF- 33pp US5388242  1995-02 Jewett  Tandem Computers Incorporated Multiprocessor system with each processor executing the same instruction sequence and hierarchical memory providing on demand page swapping
Buy PDF- 48pp US5459867  1995-10 Adams et al.  Iomega Corporation Kernels, description tables, and device drivers
Buy PDF- 50pp US5459869  1995-10 Spilo   Method for providing protected mode services for device drivers and other resident software
Buy PDF- 22pp US5675762  1997-10 Bodin et al.  International Business Machines Corporation System for locking down part of portion of memory and updating page directory with entry corresponding to part of portion of the memory locked down
Buy PDF- 21pp US5696970  1997-12 Sandage et al.  Intel Corporation Architecture for implementing PCMCIA card services under the windows operating system in enhanced mode
Buy PDF- 27pp US5758124  1998-05 Ogata et al.  Seiko Epson Corporation Computer emulator
       
Foreign References: None

Other Abstract Info: DERABS G1999-277752 DERABS G2001-145957 DERABS G2001-145957

Other References:
  • Interface Synthesis for Embedded Applications in a CoDesign Environment, Basu et al. IEEE 1997, p. 85-90.


  • Continuity Data:
    Application Number Filed Notes

    US2000000679450   is a division of
    >US1999000336889<  1999-06-18
         US6148387 issued 2000-11-14   System and method for securely utilizing basic input and output system (BIOS) services

    >US1999000336889<   is a continuation in part of
    US1997000947990  1997-10-09   (abandoned)


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