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 Title: |
US6163581:
Low-power state-sequential viterbi decoder for CDMA digital cellular applications
[ Derwent Title ]
>> View Certificate of Correction for this publication
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| Country: |
US United States of America
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| Inventor: |
Kang, Inyup; San Diego, CA
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| Assignee: |
The Regents of the University of California, Oakland, CA
other patents from UNIVERSITY OF CALIFORNIA, THE REGENTS OF (599425) (approx. 4,840)
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| Published / Filed: |
2000-12-19
/ 1998-05-05
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| Application Number: |
US1998000072654
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| IPC Code: |
Advanced:
H03M 13/41;
H04L 1/00;
H04B 1/707;
Core:
H03M 13/00;
more...
IPC-7:
H03D 13/41;
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| ECLA Code: |
H03M13/41; H03M13/41A; H04L1/00B5L;
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| U.S. Class: |
Current:
375/341;
375/262;
375/265;
704/242;
714/795;
Original:
375/341;
375/262;
375/265;
704/242;
714/795;
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| Field of Search: |
375/262,265,341
714/795
704/242
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| Government Interest: |
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
The U.S. Government has a paid-up license in this invention and the right in limited circumstances to require the patent owner to license others on reasonable terms as provided for and by the terms of Contract No. N00014-95-1-0231 awarded by the Office of Naval Research and Contract No. MIP-9201104 awarded by the National Science Foundation.
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| Priority Number: |
| 1998-05-05 |
US1998000072654 |
| 1997-05-05 |
US1997000045713P |
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| Abstract: |
A method, apparatus, and a program storage device useful in performing computations to decode a convolutionally coded sequence without resorting the use of switching elements is disclosed. The method comprises the steps of computing a first branch metric between a first input node and an output node, adding a first input path metric to the first branch metric to produce a first candidate output path metric, computing a second branch metric between a second input node and the output node, adding the second branch metric to a second path metric to derive a second candidate output path metric, and configuring a decision bit based upon the parity of the output state node state and upon whether the first candidate output path metric is greater than the second candidate output path metric. In one embodiment, a comparison between the first and the second candidate output path metrics is compared to the parity of the output node by an exclusive OR gate or a table lookup to determine the decision bit. The invention also is described by an apparatus comprising a means for performing these steps and a program storage device tangibly embodying instructions to perform the steps.
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| Attorney, Agent or Firm: |
Gates & Cooper ;
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| Primary / Asst. Examiners: |
Chin, Stephen; Rupert, Paul N
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| Maintenance Status: |
CC Certificate of Correction issued
View Certificate of Correction
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| INPADOC Legal Status: |
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| Parent Case: |
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims benefit of U.S. provisional application Ser. No. 60/045,713, filed May 5, 1997 by Inyup Kang and entitled "A LOW-POWER STATE-SEQUENTIAL VITERBI DECODER," which application is hereby incorporated by reference herein.
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| Family: |
None
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First Claim:
Show all 19 claims |
What is claimed is:
1. A method of computing a decision bit for an output node associated with an output state in a trellis butterfly, comprising the steps of:
- computing a first branch metric between a first input node and the output node, the first input node associated with a first input path metric, wherein the first branch metric defines a difference between an error free first state of a convolutionally coded sequence and a measured first state of the convolutionally coded sequence;
- adding the first input path metric to the first branch metric to produce a first candidate output path metric;
- computing a second branch metric between a second input node and the output node, the second input node associated with a second input path metric wherein the second branch metric defines a difference between an error free second state of the convolutionally coded sequence and a measured second state of the convolutionally coded sequence;
- adding the second input path metric to the second branch metric to produce a second candidate output path metric; and
- configuring the decision bit designating a path to the output node as a minimum error path based upon a parity of the output node state and upon whether the first candidate output path metric is greater than the second candidate output path metric.
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| Background / Summary: |
Show background / summary
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 7 U.S. patent(s) that reference this one
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| Foreign References: |
None
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| Other Abstract Info: |
DERABS G2001-201723
DERABS G2001-201723
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| Other References: |
Inyup Kang and Alan N. Willson, Jr., "A Low-Power State-Sequential Viterbi Decoder for CDMA Digital Cellular Applications," IEEE, 1996, pp. 272-275.
Andrew J. Viterbi, "Error Bounds for Convolutional Codes and an Asymptotically Optimum Decoding Algorithm," IEEE Transactions on Information Theory, vol. IT-13, No. 2, Apr. 1967, pp. 260-269.
Jim K. Omura, "On the Viterbi Decoding Algorithm," IEEE Transactions on Information Theory, Jan. 1969, pp. 177-179.
G. David Forney, Jr., "The Viterbi Algorithm," Proceedings of the IEEE, vol. 61, N. 3, Mar. 1973, pp. 268-278.
(11 pages)
Cited by 160 patents
Gerhard Fettweis and Heinrich Meyr, "High-Speed Parallel Viterbi Decoding: Algorithm and VLSI-Architecture," IEEE Communications Magazine, May 1991, pp. 46-55.
(10 pages)
Cited by 10 patents
[ISI abstract]
Peter J. Black and Teresa H. Meng, "A 140-Mb/s, 32-State, Radix-4 Viterbi Decoder," IEEE Journal of Solid-State Circuites, vol. 27, No. 12, Dec. 1992, pp. 1877-1885.
(9 pages)
Cited by 6 patents
[ISI abstract]
Jerrold A. Heller and Irwin Mark Jacobs, "Viterbi Decoding for Satellite and Space Communication," IEEE Transactions on Communication Technology, vol. COM-19, No. 5, Oct. 1971, pp. 835-848.
Cited by 10 patents
Andrew J. Viterbi, "Convolutional Codes and Their Performance in Communication Systems," IEEE Transactions on Communications Technology, vol. COM-19, No. 5, Oct. 1971, pp. 751-772.
Cited by 17 patents
Charles M. Rader, "Memory Management in a Viterbi Decoder," IEEE Transactions on Communications, vol. COM-29, No. 9, Sep. 1981, pp. 1399-1401.
(3 pages)
Cited by 7 patents
B.K. Min and N. Demassieux, "A Versatile Architecture for VLSI Implementation of the Viterbi Algorithm," IEEE, V2.15, 1991, pp. 1110-1104.
C. Bernard Shung, et al., "A 30-MHz Trellis Codec Chip for Partial-Response Channels," IEEE Journal of Solid-State Circuits, vol. 26, No. 12, Dec. 1991, pp. 1981-1987.
Robert Cypher and C. Bernard Shung, "Generalized Trace-Back Techniques for Survivor Memory Management in the Viterbi Algorithm," Journal of VLSI Signal Processing, 5, 85-94, 1993, pp. 85-94.
(10 pages)
Cited by 10 patents
[ISI abstract]
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