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 Title: |
US6167503:
Register and instruction controller for superscalar processor
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Jouppi, Norman P.; Palo Alto, CA
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| Assignee: |
Compaq Computer Corporation, Houston, TX
other patents from COMPAQ COMPUTER CORPORATION, INC. (755619) (approx. 2,058)
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| Published / Filed: |
2000-12-26
/ 1995-10-06
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| Application Number: |
US1995000552517
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| IPC Code: |
Advanced:
G06F 9/30;
G06F 9/38;
Core:
more...
IPC-7:
G06F 9/22;
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| ECLA Code: |
G06F9/30R4S; G06F9/38D; G06F9/38E; G06F9/38T;
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| U.S. Class: |
Current:
712/023;
712/E09.027;
712/E09.046;
712/E09.049;
712/E09.071;
Original:
712/023;
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| Field of Search: |
712/023
711/202
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| Priority Number: |
| 1995-10-06 |
US1995000552517 |
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| Abstract: |
In a superscalar computer system, a plurality of instructions are executed concurrently. The instructions being executed access data stored at addresses of the superscalar computer system. An instruction generator, such as a compiler, partitions the instructions into a plurality of sets. The plurality of sets are disjoint according to the addresses of the data to be accessed by the instructions while executing in the superscalar computer system. The system includes a plurality of clusters for executing the instructions. There is one cluster for each one of the plurality of sets of instructions. Each set of instructions is distributed to the plurality of clusters so that the addresses of the data accessed by the instructions are substantially disjoint among the clusters while immediately executing the instructions. This partitioning and distributing minimizes the number of interconnects between the clusters of the superscalar computer.
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| Attorney, Agent or Firm: |
Cesari and McKenna, LLP ;
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| Primary / Asst. Examiners: |
Eng, David Y.;
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| INPADOC Legal Status: |
Show legal status actions
Family Legal Status Report
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| Designated Country: |
DE FR GB IT NL
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| Family: |
Show 3 known family members
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First Claim:
Show all 9 claims |
What is claimed is:
1. A superscalar processor comprising:
- an instruction cache for storing instructions, some of the instructions including at least one operand, each operand having a virtual register address;
- a plurality of execution clusters for executing instructions, each execution cluster comprising a plurality of execution units, each including at least one arithmetic unit and one or more memory access units, and each execution cluster further including a plurality of registers having disjoint physical register addresses, each register corresponding to a unique one of the virtual register addresses;
- an instruction partitioning and distribution unit for fetching instructions from the instruction cache, partitioning instructions into a plurality of sets of instructions and distributing each instruction that includes at least one operand to the one of the plurality of execution clusters having the register corresponding to the virtual register address of the operand, addresses of data stored in the plurality of registers accessed by a plurality of instructions being disjoint among said plurality of execution clusters, instructions with virtual register addresses having operands assigned to corresponding physical register addresses at the time instructions are issued for execution, the instruction partitioning and distribution unit further comprising:
- a distribution buffer, the distribution buffer having a plurality of locations for storing instructions for distribution to the plurality of execution clusters; and
- means for assigning a unique serial number to each of the plurality of instructions stored in the distribution buffer, the serial numbers assigned in the order that the plurality of instructions are fetched from the instruction cache, and the serial numbers distributed to the execution clusters with the instructions;
- a central controller, connected in a communicating relationship with the instruction partitioning distribution unit and the plurality of execution clusters for distributing instructions, dependent on a predicted behavior of execution flow based on previously executed instructions, for coordinating the functioning of the superscalar processor and for monitoring the serial number of each instruction in each of the execution clusters.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
Show description
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| Forward References: |
Show 4 U.S. patent(s) that reference this one
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| Foreign References: |
None
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| Other Abstract Info: |
DERABS G1997-205563
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| Other References: |
United States Patent 5,530,817; Jun. 25, 1996.
Franklin et al., The Expandable Split Window Paradigm for Exploiting Fine-Grained Parallelism, Computer Architecture News, No. 2, May 20, 1992, pp. 58-67.
International Publication #WO 95/09394, Apr. 6, 1995, World Intellectual Property Organization, pp. 1-58 with drawings.
Keckler et al., Processor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism, Proceedings of the Annual International Symposium on Computer Architecture, Gold Coast, Australia, May 19-21, 1992, No. SYMP 19, May 19, 1992, Institute of Electrical and Electronics Engineers, pp. 202-213.
Hunt, Advanced Performance Features of the 64-bit PA-8000, Digest of Papers of the Computer Society Computer Conference (Spring) Compcon, Technologies for the Information Superhighway San Francisco, Mar. 5-9, 1995, No. Conf. 40, Mar. 5, 1995, Institute of Electrical and Electronics Engineers, pp. 123-128.
Fossum et al., Designing a VAX for High Performance, Computer Society International Conference (Compcon), Spring Meeting, Los Alamitos, Feb. 26-Mar. 2, 1990, no. Conf. 35, Feb. 26, 1990, Institute of Electrical and Electronics Engineers, pp. 36-43.
Palacharla et al., Decoupling Integer Execution in Superscalar Processors, Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Nov. 29-Dec. 1, 1995, no. Symp. 28, Nov. 29, 1995, Institute of Electrical and Electronics Engineers, pp. 285-290.
James E. Smith, "Dynamite Instruction Scheduling and the Astronautics ZS-1", IEEE Jul. 1989, pp. 21-34.
(15 pages)
Cited by 32 patents
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