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 Title: |
US6192384:
System and method for performing compound vector operations
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Dally, William J.; Stanford, CA
Rixner, Scott Whitney; Mountain View, CA
Grossman, Jeffrey P.; Cambridge, MA
Buehler, Christopher James; Cambridge, MA
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| Assignee: |
The Board of Trustees of the Leland Stanford Junior University, Stanford, CA
The Massachusetts Institute of Technology, Cambridge, MA
other patents from STANFORD UNIVERSITY (675809) (approx. 1,667)
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| Published / Filed: |
2001-02-20
/ 1998-09-14
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| Application Number: |
US1998000152763
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| IPC Code: |
Advanced:
G06F 9/30;
G06F 9/38;
Core:
more...
IPC-7:
G06F 9/28;
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| ECLA Code: |
G06F9/30R4S; G06F9/38D; G06F9/38S4; G06F9/38T;
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| U.S. Class: |
Current:
708/200;
708/003;
712/001;
712/010;
712/016;
712/020;
712/021;
712/E09.027;
712/E09.046;
712/E09.067;
712/E09.071;
Original:
708/200;
712/001;
712/010;
712/016;
712/020;
712/021;
708/003;
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| Field of Search: |
710/131-132
711/147
712/022,21,16,10
708/003,200
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| Government Interest: |
This invention was made in conjunction with U.S. Government support under U.S. Army Grant No. DABT63-96-C-0037.
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| Priority Number: |
| 1998-09-14 |
US1998000152763 |
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| Abstract: |
A processor particularly useful in multimedia applications such as image processing is based on a stream programming model and has a tiered storage architecture to minimize global bandwidth requirements. The processor has a stream register file through which the processor's functional units transfer streams to execute processor operations. Load and store instructions transfer streams between the stream register file and a stream memory; send and receive instructions transfer streams between stream register files of different processors; and operate instructions pass streams between the stream register file and computational kernels. Each of the computational kernels is capable of performing compound vector operations. A compound vector operation performs a sequence of arithmetic operations on data read from the stream register file, i.e., a global storage resource, and generates a result that is written back to the stream register file. Each function or compound vector operation is specified by an instruction sequence that specifies the arithmetic operations and data movements that are performed each cycle to carry out the compound operation. This sequence can, for example, be specified using microcode.
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| Attorney, Agent or Firm: |
Pillsbury Madison & Sutro, LLP ;
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| Primary / Asst. Examiners: |
An, Meng-Ai T.; Lin, Wen-Tai
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| INPADOC Legal Status: |
Show legal status actions
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| Family: |
None
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First Claim:
Show all 29 claims |
What is claimed:
1. A data processing system comprising:
- a controller;
- at least one arithmetic cluster capable of independently and sequentially performing compound arithmetic operations, responsive to commands directly operatively provided from the controller, on data presented at an input thereof and providing resultant processed data at an output thereof, and capable of utilizing intermediate data generated as a result of performing the operations in subsequent operations without retrieving the intermediate data from a source external to that arithmetic cluster; and
- a stream register file directly operatively coupled to the cluster and being selectively readable and writable, responsive to commands from the controller, by each of the at least one arithmetic cluster for holding the resultant processed data of the at least one arithmetic cluster.
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| Background / Summary: |
Show background / summary
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 29 U.S. patent(s) that reference this one
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