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 Title: |
US6195032:
Two-stage pipelined recycling analog-to-digital converter (ADC)
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Watson, Minh V.; Fremont, CA
Mohajeri, Hessam; San Jose, CA
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| Assignee: |
Centillium Communications, Inc., Fremont, CA
other patents from CENTILLIUM COMMUNICATIONS, INC. (771192) (approx. 9)
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| Published / Filed: |
2001-02-27
/ 1999-08-12
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| Application Number: |
US1999000373472
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| IPC Code: |
Advanced:
H03M 1/16;
H03M 1/44;
Core:
H03M 1/14;
H03M 1/38;
IPC-7:
H03M 1/14;
H03M 1/44;
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| ECLA Code: |
H03M1/16S;
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| U.S. Class: |
Current:
341/162;
341/156;
341/163;
Original:
341/162;
341/156;
341/163;
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| Field of Search: |
341/156,161,162,163
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| Priority Number: |
| 1999-08-12 |
US1999000373472 |
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| Abstract: |
An Analog-to-Digital Converter (ADC) contains two pipeline stages that operate in parallel on two different analog samples. Each pipeline stage includes two sub-stages. Each sub-stage has a low-resolution ADC element and a low-resolution DAC element. The ADC element converts the analog voltage input to the sub-stage into B digital bits, where B is a low number such as 1, 1.5, or 2. These digital bits are re-converted back to an analog DAC voltage by the DAC element. A subtractor then subtracts the analog DAC voltage from the sub-stage's analog input voltage to produce a difference voltage that represents the quantization error of the ADC/DAC elements. A multiplying amplifier multiplies the difference voltage by 2B to generate an output voltage to the next sub-stage. Each high-level pipeline stage acts as a recycling ADC, having a feedback switch that connects the output of the last sub-stage to the analog input of the first sub-stage. During successive clock periods, the first sub-stage converts B digital bits during a PH1 phase while the last sub-stage converts another B digital bits of less significance during the PH2 phase. The analog output from the last sub-stage is recycled back to the first sub-stage for the next clock and another 2B bits are converted in the next clock period. Once all of the MSB's have been converted, the last sub-stage outputs an analog residue voltage to the first sub-stage of the second pipeline stage, which then converts the LSB bits over several clock cycles using the same recycling method.
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| Attorney, Agent or Firm: |
Auvinen, Stuart T. ;
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| Primary / Asst. Examiners: |
Williams, Howard L.;
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| Maintenance Status: |
R2 Reinstated
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| INPADOC Legal Status: |
Show legal status actions
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| Family: |
None
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First Claim:
Show all 20 claims |
We claim:
1. A pipelined recycling Analog-to-Digital Converter (ADC) comprising:
- an analog sample input receiving an analog sample voltage;
- a first pipeline stage, receiving the analog sample voltage, having:
- a feedback loop that connects an output voltage of the final converter to an input of the initial converter during recycling clock periods,
- the first pipeline stage generating more-significant digital bits representing the analog sample voltage and outputting a residue voltage after several of the recycling clock periods;
- a second pipeline stage, receiving the residue voltage from the first pipeline stage, having:
- a feedback loop that connects an output voltage of the final converter to an input of the initial converter during the recycling clock periods,
- the second pipeline stage generating lower-significance digital bits representing the analog sample voltage over several of the recycling clock periods;
- wherein the initial and final converter each comprise:
- an analog input receiving an analog voltage;
- an ADC element for converting the analog voltage to digital bits;
- a digital-to-analog converter (DAC) element, coupled to the ADC element, for converting the digital bits to an analog DAC voltage;
- a subtractor, receiving the analog voltage from the analog input and receiving the analog DAC voltage, for generating a difference voltage; and
- a multiplying amplifier for increasing a scale of the difference voltage to generate an output voltage;
- whereby the feedback loops in each pipeline stage recycle analog voltages through the initial and final converters over several recycling clock periods.
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| Background / Summary: |
Show background / summary
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| Drawing Descriptions: |
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| Description: |
Show description
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| Forward References: |
Show 30 U.S. patent(s) that reference this one
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| Foreign References: |
None
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| Other References: |
Cho & Gray, "A 10b, 20 Msample/s 35 mW Pipeline A/D Converter" IEEE JSSC vol. 30, No. 3, Mar. 1995, pp. 166-72.
(7 pages)
Cited by 37 patents
[ISI abstract]
Yu & Lee, "A 2.5-v, 12-b 5-Msample/s Pipelined CMOS ADC", IEEE JSSC vol. 31 No. 12, Dec. 1996, pp. 1854-1861.
(8 pages)
Cited by 48 patents
[ISI abstract]
Li, Chin, Gray, & Castello, "A Ratio-Independent Algorithmic Analog-to-Digital Conversion Technique" IEEE JSSC vol. SC-19, No. 6, Dec. 1984, pp. 828-836.
(9 pages)
Cited by 9 patents
Sutarja & Gray, "A Pipelined 13-bit 250-Ks/s, 5-V Analog-to-digital Converter" IEEE JSSC vol.23, No. 6, Dec. 1988, pp. 1316-1323.
(8 pages)
Cited by 14 patents
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