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Title: |
US6225150:
Method for forming a TFT in a liquid crystal display
[ Derwent Title ]

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Country: |
US United States of America

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Inventor: |
Lee, Joo-Hyung; Seoul, Republic of Korea
Hong, Mun-Pyo; Sungnam-shi, Republic of Korea
Youn, Chan-Joo; Seoul, Republic of Korea
Jung, Byung-Hoo; Anyang-shi, Republic of Korea
Hwang, Chang-Won; Sungnam-shi, Republic of Korea

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Assignee: |
Samsung Electronics Co., Ltd., Seoul, Republic of Korea
other patents from SAMSUNG ELECTRONICS CO., LTD. (491065) (approx. 12,932)
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Published / Filed: |
2001-05-01
/ 1999-06-01

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Application Number: |
US1999000323030

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IPC Code: |
Advanced:
G02F 1/136;
G02F 1/1368;
H01L 21/20;
H01L 21/336;
H01L 21/8238;
H01L 27/08;
H01L 27/092;
H01L 29/423;
H01L 29/49;
H01L 29/786;
Core:
H01L 21/02;
H01L 21/70;
H01L 27/085;
H01L 29/40;
H01L 29/66;
more...
IPC-7:
H01L 21/00;

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ECLA Code: |
H01L21/77T; H01L21/336D2B; H01L29/423D2B8; H01L29/49B; H01L29/786B4B;

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U.S. Class: |
Current:
438/153;
257/E21.413;
257/E29.137;
257/E29.151;
257/E29.278;
Original:
438/153;
438/153;

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Field of Search: |
438/059,96,153,155,163,164,592,609,3,253,149

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Priority Number: |
| 1998-05-29 |
KR1998000019760 |
| 1998-11-12 |
KR1998000048365 |
| 1998-12-08 |
KR1998000053796 |

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Abstract: |
A double level gate layer with an undercut lower gate layer can be formed by using the etching rate difference between the upper gate layer and the lower gate layer in a polycrystalline Si type TFT LCD that has P-channel TFTs and N-channel TFTs. An LDD structure can be easily formed by using an upper gate layer as ion implant mask during the N-type ion implantation. LDD size is decided by the skew size between the upper gate layer and the lower gate layer. Furthermore, a photolithography step necessary for masking the ion implantation can be skipped.

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Attorney, Agent or Firm: |
Howrey Simon Arnold & White, LLP ;

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Primary / Asst. Examiners: |
Nelms, David; Nhu, David

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INPADOC Legal Status: |
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Family Legal Status Report

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Family: |
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First Claim:
Show all 5 claims |
We claim:
1. A method for forming a TFT in an LCD, comprising the steps of;
- forming a Si layer on a glass substrate;
- forming an active area by patterning the Si layer;
- forming a gate insulation layer overlying the active area;
- forming a lower metallic gate layer and an upper gate layer overlying the gate insulation layer;
- forming a photoresist pattern on the gate area of the TFT;
- forming an upper gate pattern and a lower gate pattern that has an undercut in the lower gate pattern at both source side and drain side using the photoresist pattern as etch mask;
- implanting impurities using the upper gate pattern as implant mask; and
- removing the upper gate pattern.

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Background / Summary: |
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Drawing Descriptions: |
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Description: |
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Forward References: |
Show 19 U.S. patent(s) that reference this one

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