 |
|
|
|
|
|
 Title: |
US6269435:
System and method for implementing conditional vector operations in which an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vector
[ Derwent Title ]
>> View Certificate of Correction for this publication
|
| Country: |
US United States of America
|
| |
| Inventor: |
Dally, William J.; Stanford, CA
Rixner, Scott Whitney; Mountain View, CA
Owens, John; Menlo Park, CA
Kapasi, Ujval J.; Standford, CA
|
| Assignee: |
The Board of Trustees of the Leland Stanford Junior University, Stanford, CA
The Massachusetts Institute of Technology, Cambridge, MA
other patents from STANFORD UNIVERSITY (675809) (approx. 1,667)
News, Profiles, Stocks and More about this company
|
| Published / Filed: |
2001-07-31
/ 1998-09-14
|
| Application Number: |
US1998000152944
|
| IPC Code: |
Advanced:
G06F 9/30;
G06F 9/315;
G06F 9/32;
G06F 9/38;
Core:
more...
IPC-7:
G06F 9/305;
|
| ECLA Code: |
G06F9/38T; G06F9/30R4; G06F9/30R4S; G06F9/315; G06F9/38E2; G06F9/38S4;
|
| U.S. Class: |
Current:
712/008;
345/561;
345/563;
712/005;
712/009;
712/022;
712/E09.025;
712/E09.027;
712/E09.034;
712/E09.05;
712/E09.067;
712/E09.071;
Original:
712/008;
712/005;
712/009;
712/022;
345/523;
345/524;
|
| Field of Search: |
712/005,9,22,8
345/523,524
|
| Government Interest: |
"This invention was made in conjuction with U.S. Government support under U.S. Army Grant No. DABT63-96-C-0037."
|
| Priority Number: |
| 1998-09-14 |
US1998000152944 |
|
| Abstract: |
A processor implements conditional vector operations in which an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vector. Each output vector can then be processed at full processor efficiency without cycles wasted due to branch latency. Data to be processed is divided into two groups based on whether or not they satisfy a given condition by, e.g., steering each to one of two index vectors. Once the data has been segregated in this way, subsequent processing can be performed without conditional operations, processor cycles wasted due to branch latency, incorrect speculation or execution of unnecessary instructions due to predication.
|
| Attorney, Agent or Firm: |
Pillsbury Winthrop LLP ;
|
| Primary / Asst. Examiners: |
Kim, Kenneth S.;
|
| Maintenance Status: |
CC Certificate of Correction issued
View Certificate of Correction
|
| INPADOC Legal Status: |
Show legal status actions
Family Legal Status Report
|
| Family: |
Show 2 known family members
|
First Claim:
Show all 8 claims |
What is claimed is:
1. A method of performing a conditional vector output operation in a processor, the method comprising:
- receiving electrical signals representative of an input data vector;
- generating electrical signals representative of a condition vector, the number of values in the input data vector being equal to the number of values in the condition vector, values in the input data vector and in the condition vector being in one-to-one correspondence with one another, and each value in the condition vector being a result of evaluating a predetermined conditional expression using data corresponding to a value in the input data vector; and
- generating electrical signals representative of an output vector containing values in the input data vector for which corresponding values in the condition vector are equal to a predetermined value;
- wherein generating the output vector includes
- maintaining a running index indicative of a last-added value in the output vector;
- for each value, in a group of values from the input data vector, corresponding to a condition value in the condition vector which is equal to the predetermined value, calculating an absolute index indicative of a position of the value in the group within an output vector, the absolute index corresponding to the condition value and the running index; and
- including each of the values within the group in an output vector corresponding to condition vector values equaling the predetermined value, at respective positions denoted by the absolute indices.
|
| Background / Summary: |
Show background / summary
|
| Drawing Descriptions: |
Show drawing descriptions
|
| Description: |
Show description
|
| Forward References: |
Show 3 U.S. patent(s) that reference this one
|
