 |
|
|
|
|
|
 Title: |
US6275109:
Low noise microphone preamplifier
[ Derwent Title ]
|
| Country: |
US United States of America
|
| |
| Inventor: |
Tang, Zhi-Long; Allentown, PA
|
| Assignee: |
Agere Systems Guardian Corp.
other patents from AGERE SYSTEMS GUARDIAN CORP. (781528) (approx. 646)
News, Profiles, Stocks and More about this company
|
| Published / Filed: |
2001-08-14
/ 1999-08-02
|
| Application Number: |
US1999000366117
|
| IPC Code: |
Advanced:
H03F 3/187;
H03F 3/45;
Core:
H03F 3/181;
more...
IPC-7:
H03F 3/14;
H03F 3/45;
|
| ECLA Code: |
H03F3/187; H03F3/45S1K; H03F3/45S1B1;
|
| U.S. Class: |
Current:
330/261;
330/253;
330/307;
Original:
330/261;
330/253;
330/307;
|
| Field of Search: |
330/252,253,261,307
|
| Priority Number: |
| 1999-08-02 |
US1999000366117 |
|
| Abstract: |
An integrated circuit preamplifier amplifies an input signal comprising first and second differential input signals to provide an amplified output signal comprising first and second differential output signals. A biasing circuit of the preamplifier provides a bias current. An open-loop differential amplifier of the preamplifier is coupled to the biasing circuit. The differential amplifier includes a differential amplifier pair having first and second differential amplifying transistors, which are coupled at respective gate terminals to the first and second differential input signals. Each of the amplifying transistors are coupled in open-loop configuration at a drain terminal to a respective load resistor coupled to ground, and the source terminals of the amplifying transistors are coupled together to receive the bias current. The first and second differential output signals are formed across the respective first and second load resistors.
|
| Attorney, Agent or Firm: |
Duane, Morris & Heckscher LLP ;
|
| Primary / Asst. Examiners: |
Pascal, Robert; Nguyen, Patricia T.
|
| INPADOC Legal Status: |
Show legal status actions
|
| Family: |
None
|
First Claim:
Show all 6 claims |
What is claimed is:
1. An integrated circuit comprising a preamplifier for amplifying an input signal comprising first and second non-amplified differential input signals to provide an amplified output signal comprising first and second differential output signals, the preamplifier comprising:
- (a) a biasing circuit for providing a bias current, said biasing circuit comprising:
- a bias resistor and first current mirror transistor for producing a preliminary bias current which is proportional to the value of the bias resistor; and
- a second current mirror transistor coupled to the first current mirror transistor to form a current mirror which generates with the second current mirror transistor the bias current, wherein the bias current is proportional to the preliminary biasing current; and
- (b) an open-loop differential amplifier, coupled to the biasing circuit, comprising a differential amplifier pair comprising first and second differential amplifying transistors coupled at respective gate terminals to the first and second differential input signals, wherein the first and second amplifying transistors are coupled in open-loop configuration at respective drain terminals to first and second load resistors coupled to ground, respectively, wherein respective source terminals of the amplifying transistors are coupled together to receive the bias current, wherein the first and second differential output signals are formed across the first and second load resistors, respectively, wherein the preamplifier has a gain that depends at least in part on the ratio between the resistance value of the first and second load resistors and the resistance value of the bias resistor.
|
| Background / Summary: |
Show background / summary
|
| Drawing Descriptions: |
Show drawing descriptions
|
| Description: |
Show description
|
| Forward References: |
Show 5 U.S. patent(s) that reference this one
|
|
|
|
|
|
|
| Foreign References: |
None
|
| Other References: |
IEEE Journal of Solid-State Circuits, vol. 33, No. 8, Aug. 1998, "A High-Performance Analog Front-End 14-Bit Codec for 2.7-V Digital Cellular Phones", pp. 1158-1166.
(10 pages)
[ISI abstract]
Paul R. Gray, Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, Second Edition, John Wiley & Sons, New York, Chichester, Brisbane, Toronto, Singapore, pp. 388-391, 394-395, & 708.
|
|
 Nominate this for the Gallery...
|
|
