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 Title: |
US6281727:
Fine-tuning phase-locked loop PLL using variable resistor between dual PLL loops
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Hattori, Hide; Palo Alto, CA
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| Assignee: |
Pericom Semiconductor Corp., San Jose, CA
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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| Published / Filed: |
2001-08-28
/ 2000-10-05
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| Application Number: |
US2000000679684
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| IPC Code: |
Advanced:
H03L 7/23;
H03L 7/089;
Core:
H03L 7/16;
more...
IPC-7:
H03L 7/06;
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| ECLA Code: |
H03L7/23;
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| U.S. Class: |
Current:
327/156;
375/376;
Original:
327/156;
375/376;
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| Field of Search: |
327/146,147,148,150,155,156,157,159
375/373-376
331/017
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| Priority Number: |
| 2000-10-05 |
US2000000679684 |
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| Abstract: |
A clock generator uses two PLL loops and a variable resistor to generate a variable output frequency from a single fixed-frequency reference clock. Each PLL loop receives the reference clock and phase-compares it with a feedback clock. The feedback clock in one loop is slightly faster in frequency than the feedback clock in the second loop. The input voltages to voltage-controlled oscillators (VCOs) in the two loops thus vary slightly. A variable resistor is connected between the two inputs to the VCOs. The variable resistor has a center tap that can be selected from locations along the variable resistor. The center tap voltage is input to a final VCO that generates the variable output frequency. The output frequency is varied by selecting the center tap's location along the variable resistor. The variable resistor can be constructed from a series of sub-resistors with the center-tap location chosen by select transistors acting as a multiplexer.
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| Attorney, Agent or Firm: |
Auvinen, Stuart T. ;
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| Primary / Asst. Examiners: |
Ton, My-Trang Nu;
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| Maintenance Status: |
E2 Expired Check current status
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| INPADOC Legal Status: |
Show legal status actions
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| Family: |
None
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First Claim:
Show all 20 claims |
I claim:
1. A dual-loop clock generator comprising:
- a reference-clock input, having a reference frequency;
- a first phase-locked loop, receiving the reference-clock input, for generating a first feedback clock having a first feedback frequency, the first phase-locked loop phase comparing the reference-clock input to the first feedback clock, the first phase-locked loop charging and discharging a first capacitance in response to phase comparison to adjust a first voltage;
- a second phase-locked loop, receiving the reference-clock input, for generating a second feedback clock having a second feedback frequency, the second phase-locked loop phase comparing the reference-clock input to the second feedback clock, the second phase-locked loop charging and discharging a second capacitance in response to phase comparison to adjust a second voltage;
- wherein the second voltage differs from the first voltage;
- a variable resistor coupled between the first voltage and the second voltage, the variable resistor having a selectable center tap, wherein an output resistance from the first voltage to the selectable center tap is selectable among a range of fractional resistances of the variable resistor; and
- an output-clock generator, coupled to the variable resistor by selectable center tap, for generating an output clock having an output frequency, the output frequency determined by the selectable center tap,
whereby the output frequency is determined by the selectable center tap of the variable resistor between the first and second phase-locked loops.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 6 U.S. patent(s) that reference this one
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